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[X86] Fix register parsing in .seh_* in Intel syntax

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Previously, the parser checked for a '%' prefix to indicate a register.
In Intel syntax mode, LLVM does not print a '%' prefix on registers, so
LLVM could not parse its own assembly output. Instead, require that
register numbers be integer literals, or at least start with an integer
literal, which is consistent with .cfi_* directive register parsing.

llvm-svn: 375287
This commit is contained in:
Reid Kleckner 2019-10-18 21:01:41 +00:00
parent a02ae49a6b
commit e262abe247
2 changed files with 49 additions and 4 deletions
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7
lib/Target/X86/AsmParser/X86AsmParser.cpp
View File

@ -3749,11 +3749,10 @@ bool X86AsmParser::parseSEHRegisterNumber(unsigned RegClassID,
SMLoc startLoc = getLexer().getLoc();
const MCRegisterInfo *MRI = getContext().getRegisterInfo();
// A percent indicates a symbolic register name. Parse it as usual and check
// the register class.
if (getLexer().is(AsmToken::Percent)) {
// Try parsing the argument as a register first.
if (getLexer().getTok().isNot(AsmToken::Integer)) {
SMLoc endLoc;
if (getParser().getTargetParser().ParseRegister(RegNo, startLoc, endLoc))
if (ParseRegister(RegNo, startLoc, endLoc))
return true;
if (!X86MCRegisterClasses[RegClassID].contains(RegNo)) {

46
test/MC/AsmParser/directive_seh.s
View File

@ -1,5 +1,9 @@
# RUN: llvm-mc -triple x86_64-pc-win32 %s | FileCheck %s
# Round trip via intel syntax printing and back.
# RUN: llvm-mc -triple x86_64-pc-win32 %s -output-asm-variant=1 | \
# RUN: llvm-mc -triple x86_64-pc-win32 -x86-asm-syntax=intel | FileCheck %s
.text
.globl func
.def func; .scl 2; .type 32; .endef
@ -51,3 +55,45 @@ func:
ret
.seh_endproc
# CHECK: .seh_endproc
# Re-run more or less the same test, but with intel syntax. Previously LLVM
# required percent prefixing in the .seh_* directives that take registers.
.intel_syntax noprefix
.text
.globl func_intel
.def func_intel; .scl 2; .type 32; .endef
.seh_proc func_intel
# CHECK: .seh_proc func_intel
func_intel:
sub RSP, 24
.seh_stackalloc 24
# CHECK: .seh_stackalloc 24
mov [16+RSP], RSI
.seh_savereg rsi, 16
# CHECK: .seh_savereg %rsi, 16
.seh_savereg 6, 16
# CHECK: .seh_savereg %rsi, 16
movups [RSP], XMM8
.seh_savexmm XMM8, 0
# CHECK: .seh_savexmm %xmm8, 0
.seh_savexmm 8, 0
# CHECK: .seh_savexmm %xmm8, 0
push rbx
.seh_pushreg rbx
# CHECK: .seh_pushreg %rbx
.seh_pushreg 3
# CHECK: .seh_pushreg %rbx
mov rbx, rsp
.seh_setframe rbx, 0
# CHECK: .seh_setframe %rbx, 0
.seh_endprologue
# CHECK: .seh_endprologue
.seh_handler __C_specific_handler, @except
# CHECK: .seh_handler __C_specific_handler, @except
.seh_handlerdata
# CHECK-NOT: .section{{.*}}.xdata
# CHECK: .seh_handlerdata
.long 0
.text
.seh_endproc