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https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-24 11:42:57 +01:00
reverting patch 176508.
llvm-svn: 176513
This commit is contained in:
Jyotsna Verma
parent
ef3cf2b345
commit
e27b88fb08
@ -1024,14 +1024,6 @@ SDValue HexagonTargetLowering::LowerGLOBALADDRESS(SDValue Op,
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return DAG.getNode(HexagonISD::CONST32, dl, getPointerTy(), Result);
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}
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SDValue
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HexagonTargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
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const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
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SDValue BA_SD = DAG.getTargetBlockAddress(BA, MVT::i32);
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DebugLoc dl = Op.getDebugLoc();
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return DAG.getNode(HexagonISD::CONST32_GP, dl, getPointerTy(), BA_SD);
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}
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//===----------------------------------------------------------------------===//
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// TargetLowering Implementation
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//===----------------------------------------------------------------------===//
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@ -1305,7 +1297,6 @@ HexagonTargetLowering::HexagonTargetLowering(HexagonTargetMachine
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// Custom legalize GlobalAddress nodes into CONST32.
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setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
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setOperationAction(ISD::GlobalAddress, MVT::i8, Custom);
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setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
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// Truncate action?
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setOperationAction(ISD::TRUNCATE, MVT::i64, Expand);
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@ -1468,8 +1459,6 @@ HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const {
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switch (Opcode) {
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default: return 0;
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case HexagonISD::CONST32: return "HexagonISD::CONST32";
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case HexagonISD::CONST32_GP: return "HexagonISD::CONST32_GP";
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case HexagonISD::CONST32_Int_Real: return "HexagonISD::CONST32_Int_Real";
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case HexagonISD::ADJDYNALLOC: return "HexagonISD::ADJDYNALLOC";
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case HexagonISD::CMPICC: return "HexagonISD::CMPICC";
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case HexagonISD::CMPFCC: return "HexagonISD::CMPFCC";
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@ -1518,7 +1507,6 @@ HexagonTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG);
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case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
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case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG);
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case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
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case ISD::VASTART: return LowerVASTART(Op, DAG);
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case ISD::BR_JT: return LowerBR_JT(Op, DAG);
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@ -27,7 +27,6 @@ namespace llvm {
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CONST32,
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CONST32_GP, // For marking data present in GP.
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CONST32_Int_Real,
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FCONST32,
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SETCC,
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ADJDYNALLOC,
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@ -107,7 +106,6 @@ namespace llvm {
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const;
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SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const;
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@ -2076,10 +2076,6 @@ def CONST32_Int_Real : LDInst2<(outs IntRegs:$dst), (ins i32imm:$global),
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"$dst = CONST32(#$global)",
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[(set (i32 IntRegs:$dst), imm:$global) ]>;
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// Map BlockAddress lowering to CONST32_Int_Real
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def : Pat<(HexagonCONST32_GP tblockaddress:$addr),
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(CONST32_Int_Real tblockaddress:$addr)>;
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let isReMaterializable = 1, isMoveImm = 1 in
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def CONST32_Label : LDInst2<(outs IntRegs:$dst), (ins bblabel:$label),
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"$dst = CONST32($label)",
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@ -3050,11 +3046,6 @@ def BR_JT : JRInst<(outs), (ins IntRegs:$src),
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"jumpr $src",
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[(HexagonBR_JT (i32 IntRegs:$src))]>;
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let isBranch=1, isIndirectBranch=1, isTerminator=1 in
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def BRIND : JRInst<(outs), (ins IntRegs:$src),
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"jumpr $src",
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[(brind (i32 IntRegs:$src))]>;
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def HexagonWrapperJT: SDNode<"HexagonISD::WrapperJT", SDTIntUnaryOp>;
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def : Pat<(HexagonWrapperJT tjumptable:$dst),
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@ -3790,11 +3790,6 @@ def TFRI_V4 : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$src1),
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[(set IntRegs:$dst, (HexagonCONST32 tglobaladdr:$src1))]>,
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Requires<[HasV4T]>;
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// Transfer a block address into a register
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def : Pat<(HexagonCONST32_GP tblockaddress:$src1),
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(TFRI_V4 tblockaddress:$src1)>,
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Requires<[HasV4T]>;
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let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
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def TFRI_cPt_V4 : ALU32_ri<(outs IntRegs:$dst),
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(ins PredRegs:$src1, globaladdress:$src2),
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@ -1,64 +0,0 @@
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; CHECK: r{{[0-9]+}} = CONST32(#.LJTI{{[0-9]+_[0-9]+}})
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; CHECK: r{{[0-9]+}} = memw(r{{[0-9]+}}+r{{[0-9]+<<#[0-9]+}})
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; CHECK: jumpr r{{[0-9]+}}
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define void @main() #0 {
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entry:
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%ret = alloca i32, align 4
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br label %while.body
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while.body:
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%ret.0.load17 = load volatile i32* %ret, align 4
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switch i32 %ret.0.load17, label %label6 [
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i32 0, label %label0
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i32 1, label %label1
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i32 2, label %label2
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i32 3, label %label3
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i32 4, label %label4
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i32 5, label %label5
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]
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label0:
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%ret.0.load18 = load volatile i32* %ret, align 4
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%inc = add nsw i32 %ret.0.load18, 1
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store volatile i32 %inc, i32* %ret, align 4
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br label %while.body
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label1:
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%ret.0.load19 = load volatile i32* %ret, align 4
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%inc2 = add nsw i32 %ret.0.load19, 1
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store volatile i32 %inc2, i32* %ret, align 4
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br label %while.body
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label2:
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%ret.0.load20 = load volatile i32* %ret, align 4
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%inc4 = add nsw i32 %ret.0.load20, 1
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store volatile i32 %inc4, i32* %ret, align 4
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br label %while.body
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label3:
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%ret.0.load21 = load volatile i32* %ret, align 4
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%inc6 = add nsw i32 %ret.0.load21, 1
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store volatile i32 %inc6, i32* %ret, align 4
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br label %while.body
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label4:
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%ret.0.load22 = load volatile i32* %ret, align 4
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%inc8 = add nsw i32 %ret.0.load22, 1
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store volatile i32 %inc8, i32* %ret, align 4
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br label %while.body
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label5:
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%ret.0.load23 = load volatile i32* %ret, align 4
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%inc10 = add nsw i32 %ret.0.load23, 1
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store volatile i32 %inc10, i32* %ret, align 4
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br label %while.body
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label6:
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store volatile i32 0, i32* %ret, align 4
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br label %while.body
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}
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attributes #0 = { noreturn nounwind "target-cpu"="hexagonv4" }
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@ -1,14 +0,0 @@
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; RUN: llc -march=hexagon < %s | FileCheck %s
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;CHECK: jumpr r{{[0-9]+}}
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define i32 @check_indirect_br(i8* %target) nounwind {
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entry:
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indirectbr i8* %target, [label %test_label]
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test_label:
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br label %ret
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ret:
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ret i32 -1
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}
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