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Use PMADDWD to expand reduction in a loop
Summary: PMADDWD can help improve 8/16 bit integer mutliply-add operation performance for cases like: for (int i = 0; i < count; i++) a += x[i] * y[i]; Reviewers: wmi, davidxl, hfinkel, RKSimon, zvi, mkuper Reviewed By: mkuper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D31679 llvm-svn: 299776
This commit is contained in:
Dehao Chen
parent
25a9da5485
commit
e2d4caaef2
@ -34618,6 +34618,51 @@ static SDValue combineAddOrSubToADCOrSBB(SDNode *N, SelectionDAG &DAG) {
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DAG.getConstant(0, DL, VT), NewCmp);
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DAG.getConstant(0, DL, VT), NewCmp);
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}
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}
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static SDValue combineLoopMAddPattern(SDNode *N, SelectionDAG &DAG,
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const X86Subtarget &Subtarget) {
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SDValue MulOp = N->getOperand(0);
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SDValue Phi = N->getOperand(1);
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if (MulOp.getOpcode() != ISD::MUL)
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std::swap(MulOp, Phi);
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if (MulOp.getOpcode() != ISD::MUL)
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return SDValue();
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ShrinkMode Mode;
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if (!canReduceVMulWidth(MulOp.getNode(), DAG, Mode))
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return SDValue();
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EVT VT = N->getValueType(0);
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unsigned RegSize = 128;
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if (Subtarget.hasBWI())
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RegSize = 512;
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else if (Subtarget.hasAVX2())
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RegSize = 256;
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unsigned VectorSize = VT.getVectorNumElements() * 16;
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// If the vector size is less than 128, or greater than the supported RegSize,
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// do not use PMADD.
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if (VectorSize < 128 || VectorSize > RegSize)
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return SDValue();
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SDLoc DL(N);
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EVT ReducedVT = EVT::getVectorVT(*DAG.getContext(), MVT::i16,
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VT.getVectorNumElements());
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EVT MAddVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
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VT.getVectorNumElements() / 2);
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// Shrink the operands of mul.
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SDValue N0 = DAG.getNode(ISD::TRUNCATE, DL, ReducedVT, MulOp->getOperand(0));
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SDValue N1 = DAG.getNode(ISD::TRUNCATE, DL, ReducedVT, MulOp->getOperand(1));
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// Madd vector size is half of the original vector size
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SDValue Madd = DAG.getNode(X86ISD::VPMADDWD, DL, MAddVT, N0, N1);
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// Fill the rest of the output with 0
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SDValue Zero = getZeroVector(Madd.getSimpleValueType(), Subtarget, DAG, DL);
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SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Madd, Zero);
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return DAG.getNode(ISD::ADD, DL, VT, Concat, Phi);
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}
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static SDValue combineLoopSADPattern(SDNode *N, SelectionDAG &DAG,
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static SDValue combineLoopSADPattern(SDNode *N, SelectionDAG &DAG,
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const X86Subtarget &Subtarget) {
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const X86Subtarget &Subtarget) {
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SDLoc DL(N);
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SDLoc DL(N);
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@ -34695,6 +34740,8 @@ static SDValue combineAdd(SDNode *N, SelectionDAG &DAG,
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if (Flags->hasVectorReduction()) {
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if (Flags->hasVectorReduction()) {
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if (SDValue Sad = combineLoopSADPattern(N, DAG, Subtarget))
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if (SDValue Sad = combineLoopSADPattern(N, DAG, Subtarget))
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return Sad;
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return Sad;
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if (SDValue MAdd = combineLoopMAddPattern(N, DAG, Subtarget))
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return MAdd;
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}
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}
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EVT VT = N->getValueType(0);
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EVT VT = N->getValueType(0);
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SDValue Op0 = N->getOperand(0);
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SDValue Op0 = N->getOperand(0);
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103
test/CodeGen/X86/madd.ll
Normal file
103
test/CodeGen/X86/madd.ll
Normal file
@ -0,0 +1,103 @@
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=AVX512
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw | FileCheck %s --check-prefix=AVX512
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;SSE2-label: @_Z10test_shortPsS_i
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;SSE2: movdqu
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;SSE2-NEXT: movdqu
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;SSE2-NEXT: pmaddwd
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;SSE2-NEXT: paddd
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;AVX2-label: @_Z10test_shortPsS_i
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;AVX2: vmovdqu
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;AVX2-NEXT: vpmaddwd
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;AVX2-NEXT: vinserti128
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;AVX2-NEXT: vpaddd
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;AVX512-label: @_Z10test_shortPsS_i
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;AVX512: vmovdqu
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;AVX512-NEXT: vpmaddwd
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;AVX512-NEXT: vinserti128
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;AVX512-NEXT: vpaddd
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define i32 @_Z10test_shortPsS_i(i16* nocapture readonly, i16* nocapture readonly, i32) local_unnamed_addr #0 {
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entry:
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%3 = zext i32 %2 to i64
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br label %vector.body
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vector.body:
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%index = phi i64 [ %index.next, %vector.body ], [ 0, %entry ]
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%vec.phi = phi <8 x i32> [ %11, %vector.body ], [ zeroinitializer, %entry ]
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%4 = getelementptr inbounds i16, i16* %0, i64 %index
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%5 = bitcast i16* %4 to <8 x i16>*
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%wide.load = load <8 x i16>, <8 x i16>* %5, align 2
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%6 = sext <8 x i16> %wide.load to <8 x i32>
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%7 = getelementptr inbounds i16, i16* %1, i64 %index
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%8 = bitcast i16* %7 to <8 x i16>*
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%wide.load14 = load <8 x i16>, <8 x i16>* %8, align 2
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%9 = sext <8 x i16> %wide.load14 to <8 x i32>
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%10 = mul nsw <8 x i32> %9, %6
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%11 = add nsw <8 x i32> %10, %vec.phi
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%index.next = add i64 %index, 8
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%12 = icmp eq i64 %index.next, %3
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br i1 %12, label %middle.block, label %vector.body
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middle.block:
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%rdx.shuf = shufflevector <8 x i32> %11, <8 x i32> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
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%bin.rdx = add <8 x i32> %11, %rdx.shuf
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%rdx.shuf15 = shufflevector <8 x i32> %bin.rdx, <8 x i32> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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%bin.rdx16 = add <8 x i32> %bin.rdx, %rdx.shuf15
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%rdx.shuf17 = shufflevector <8 x i32> %bin.rdx16, <8 x i32> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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%bin.rdx18 = add <8 x i32> %bin.rdx16, %rdx.shuf17
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%13 = extractelement <8 x i32> %bin.rdx18, i32 0
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ret i32 %13
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}
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;AVX2-label: @_Z9test_charPcS_i
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;AVX2: vpmovsxbw
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;AVX2-NEXT: vpmovsxbw
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;AVX2-NEXT: vpmaddwd
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;AVX2-NEXT: vpaddd
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;AVX512-label: @_Z9test_charPcS_i
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;AVX512: vpmovsxbw
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;AVX512-NEXT: vpmovsxbw
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;AVX512-NEXT: vpmaddwd
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;AVX512-NEXT: vinserti64x4
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;AVX512-NEXT: vpaddd
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define i32 @_Z9test_charPcS_i(i8* nocapture readonly, i8* nocapture readonly, i32) local_unnamed_addr #0 {
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entry:
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%3 = zext i32 %2 to i64
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br label %vector.body
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vector.body:
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%index = phi i64 [ %index.next, %vector.body ], [ 0, %entry ]
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%vec.phi = phi <16 x i32> [ %11, %vector.body ], [ zeroinitializer, %entry ]
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%4 = getelementptr inbounds i8, i8* %0, i64 %index
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%5 = bitcast i8* %4 to <16 x i8>*
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%wide.load = load <16 x i8>, <16 x i8>* %5, align 1
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%6 = sext <16 x i8> %wide.load to <16 x i32>
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%7 = getelementptr inbounds i8, i8* %1, i64 %index
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%8 = bitcast i8* %7 to <16 x i8>*
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%wide.load14 = load <16 x i8>, <16 x i8>* %8, align 1
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%9 = sext <16 x i8> %wide.load14 to <16 x i32>
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%10 = mul nsw <16 x i32> %9, %6
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%11 = add nsw <16 x i32> %10, %vec.phi
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%index.next = add i64 %index, 16
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%12 = icmp eq i64 %index.next, %3
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br i1 %12, label %middle.block, label %vector.body
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middle.block:
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%rdx.shuf = shufflevector <16 x i32> %11, <16 x i32> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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%bin.rdx = add <16 x i32> %11, %rdx.shuf
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%rdx.shuf15 = shufflevector <16 x i32> %bin.rdx, <16 x i32> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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%bin.rdx16 = add <16 x i32> %bin.rdx, %rdx.shuf15
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%rdx.shuf17 = shufflevector <16 x i32> %bin.rdx16, <16 x i32> undef, <16 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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%bin.rdx18 = add <16 x i32> %bin.rdx16, %rdx.shuf17
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%rdx.shuf19 = shufflevector <16 x i32> %bin.rdx18, <16 x i32> undef, <16 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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%bin.rdx20 = add <16 x i32> %bin.rdx18, %rdx.shuf19
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%13 = extractelement <16 x i32> %bin.rdx20, i32 0
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ret i32 %13
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}
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