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Preserve the original ordering when a CSR has multiple aliases.
Previously, these aliases would be ordered alphabetically. (BH, BL) Print out the computed allocation orders. llvm-svn: 132580
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@ -14,10 +14,14 @@
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//
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "regalloc"
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#include "RegisterClassInfo.h"
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#include "RegisterClassInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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using namespace llvm;
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RegisterClassInfo::RegisterClassInfo() : Tag(0), MF(0), TRI(0), CalleeSaved(0)
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RegisterClassInfo::RegisterClassInfo() : Tag(0), MF(0), TRI(0), CalleeSaved(0)
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@ -86,8 +90,9 @@ void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
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if (Reserved.test(PhysReg))
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if (Reserved.test(PhysReg))
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continue;
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continue;
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if (unsigned CSR = CSRNum[PhysReg])
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if (unsigned CSR = CSRNum[PhysReg])
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// PhysReg aliases a CSR, save it for later.
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// PhysReg aliases a CSR, save it for later. Provide a (CSR, N) sort key
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CSRAlias.push_back(std::make_pair(CSR, PhysReg));
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// to preserve the original ordering of multiple aliases of the same CSR.
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CSRAlias.push_back(std::make_pair((CSR << 16) + (I - AOB), PhysReg));
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else
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else
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RCI.Order[N++] = PhysReg;
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RCI.Order[N++] = PhysReg;
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}
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}
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@ -101,6 +106,13 @@ void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
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for (unsigned i = 0, e = CSRAlias.size(); i != e; ++i)
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for (unsigned i = 0, e = CSRAlias.size(); i != e; ++i)
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RCI.Order[N++] = CSRAlias[i].second;
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RCI.Order[N++] = CSRAlias[i].second;
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DEBUG({
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dbgs() << "AllocationOrder(" << RC->getName() << ") = [";
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for (unsigned I = 0; I != N; ++I)
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dbgs() << ' ' << PrintReg(RCI.Order[I], TRI);
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dbgs() << " ]\n";
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});
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// RCI is now up-to-date.
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// RCI is now up-to-date.
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RCI.Tag = Tag;
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RCI.Tag = Tag;
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}
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}
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