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Change the x86 assembly output to use tab characters to separate the

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mnemonics from their operands instead of single spaces. This makes the
assembly output a little more consistent with various other compilers
(f.e. GCC), and slightly easier to read. Also, update the regression
tests accordingly.

llvm-svn: 40648
This commit is contained in:
Dan Gohman 2007-07-31 20:11:57 +00:00
parent 4251f42689
commit e3464e6bec
35 changed files with 1163 additions and 1163 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

114
lib/Target/X86/X86InstrFPStack.td
View File

@ -165,9 +165,9 @@ def _Fp64m32: FpI<(outs RFP64:$dst), (ins RFP64:$src1, f32mem:$src2), OneArgFPRW
[(set RFP64:$dst,
(OpNode RFP64:$src1, (extloadf32 addr:$src2)))]>;
def _F32m : FPI<0xD8, fp, (outs), (ins f32mem:$src),
!strconcat("f", !strconcat(asmstring, "{s} $src"))>;
!strconcat("f", !strconcat(asmstring, "{s}\t$src"))>;
def _F64m : FPI<0xDC, fp, (outs), (ins f64mem:$src),
!strconcat("f", !strconcat(asmstring, "{l} $src"))>;
!strconcat("f", !strconcat(asmstring, "{l}\t$src"))>;
// ST(0) = ST(0) + [memint]
def _FpI16m32 : FpI<(outs RFP32:$dst), (ins RFP32:$src1, i16mem:$src2), OneArgFPRW,
[(set RFP32:$dst, (OpNode RFP32:$src1,
@ -182,9 +182,9 @@ def _FpI32m64 : FpI<(outs RFP64:$dst), (ins RFP64:$src1, i32mem:$src2), OneArgFP
[(set RFP64:$dst, (OpNode RFP64:$src1,
(X86fild addr:$src2, i32)))]>;
def _FI16m : FPI<0xDE, fp, (outs), (ins i16mem:$src),
!strconcat("fi", !strconcat(asmstring, "{s} $src"))>;
!strconcat("fi", !strconcat(asmstring, "{s}\t$src"))>;
def _FI32m : FPI<0xDA, fp, (outs), (ins i32mem:$src),
!strconcat("fi", !strconcat(asmstring, "{l} $src"))>;
!strconcat("fi", !strconcat(asmstring, "{l}\t$src"))>;
}
defm ADD : FPBinary_rr<fadd>;
@ -208,24 +208,24 @@ class FPrST0PInst<bits<8> o, string asm>
// NOTE: GAS and apparently all other AT&T style assemblers have a broken notion
// of some of the 'reverse' forms of the fsub and fdiv instructions. As such,
// we have to put some 'r's in and take them out of weird places.
def ADD_FST0r : FPST0rInst <0xC0, "fadd $op">;
def ADD_FrST0 : FPrST0Inst <0xC0, "fadd {%st(0), $op|$op, %ST(0)}">;
def ADD_FPrST0 : FPrST0PInst<0xC0, "faddp $op">;
def SUBR_FST0r : FPST0rInst <0xE8, "fsubr $op">;
def SUB_FrST0 : FPrST0Inst <0xE8, "fsub{r} {%st(0), $op|$op, %ST(0)}">;
def SUB_FPrST0 : FPrST0PInst<0xE8, "fsub{r}p $op">;
def SUB_FST0r : FPST0rInst <0xE0, "fsub $op">;
def SUBR_FrST0 : FPrST0Inst <0xE0, "fsub{|r} {%st(0), $op|$op, %ST(0)}">;
def SUBR_FPrST0 : FPrST0PInst<0xE0, "fsub{|r}p $op">;
def MUL_FST0r : FPST0rInst <0xC8, "fmul $op">;
def MUL_FrST0 : FPrST0Inst <0xC8, "fmul {%st(0), $op|$op, %ST(0)}">;
def MUL_FPrST0 : FPrST0PInst<0xC8, "fmulp $op">;
def DIVR_FST0r : FPST0rInst <0xF8, "fdivr $op">;
def DIV_FrST0 : FPrST0Inst <0xF8, "fdiv{r} {%st(0), $op|$op, %ST(0)}">;
def DIV_FPrST0 : FPrST0PInst<0xF8, "fdiv{r}p $op">;
def DIV_FST0r : FPST0rInst <0xF0, "fdiv $op">;
def DIVR_FrST0 : FPrST0Inst <0xF0, "fdiv{|r} {%st(0), $op|$op, %ST(0)}">;
def DIVR_FPrST0 : FPrST0PInst<0xF0, "fdiv{|r}p $op">;
def ADD_FST0r : FPST0rInst <0xC0, "fadd\t$op">;
def ADD_FrST0 : FPrST0Inst <0xC0, "fadd\t{%st(0), $op|$op, %ST(0)}">;
def ADD_FPrST0 : FPrST0PInst<0xC0, "faddp\t$op">;
def SUBR_FST0r : FPST0rInst <0xE8, "fsubr\t$op">;
def SUB_FrST0 : FPrST0Inst <0xE8, "fsub{r}\t{%st(0), $op|$op, %ST(0)}">;
def SUB_FPrST0 : FPrST0PInst<0xE8, "fsub{r}p\t$op">;
def SUB_FST0r : FPST0rInst <0xE0, "fsub\t$op">;
def SUBR_FrST0 : FPrST0Inst <0xE0, "fsub{|r}\t{%st(0), $op|$op, %ST(0)}">;
def SUBR_FPrST0 : FPrST0PInst<0xE0, "fsub{|r}p\t$op">;
def MUL_FST0r : FPST0rInst <0xC8, "fmul\t$op">;
def MUL_FrST0 : FPrST0Inst <0xC8, "fmul\t{%st(0), $op|$op, %ST(0)}">;
def MUL_FPrST0 : FPrST0PInst<0xC8, "fmulp\t$op">;
def DIVR_FST0r : FPST0rInst <0xF8, "fdivr\t$op">;
def DIV_FrST0 : FPrST0Inst <0xF8, "fdiv{r}\t{%st(0), $op|$op, %ST(0)}">;
def DIV_FPrST0 : FPrST0PInst<0xF8, "fdiv{r}p\t$op">;
def DIV_FST0r : FPST0rInst <0xF0, "fdiv\t$op">;
def DIVR_FrST0 : FPrST0Inst <0xF0, "fdiv{|r}\t{%st(0), $op|$op, %ST(0)}">;
def DIVR_FPrST0 : FPrST0PInst<0xF0, "fdiv{|r}p\t$op">;
// Unary operations.
multiclass FPUnary<SDNode OpNode, bits<8> opcode, string asmstring> {
@ -270,21 +270,21 @@ defm CMOVNP : FPCMov<X86_COND_NP>;
// These are not factored because there's no clean way to pass DA/DB.
def CMOVB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins),
"fcmovb {$op, %st(0)|%ST(0), $op}">, DA;
"fcmovb\t{$op, %st(0)|%ST(0), $op}">, DA;
def CMOVBE_F : FPI<0xD0, AddRegFrm, (outs RST:$op), (ins),
"fcmovbe {$op, %st(0)|%ST(0), $op}">, DA;
"fcmovbe\t{$op, %st(0)|%ST(0), $op}">, DA;
def CMOVE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins),
"fcmove {$op, %st(0)|%ST(0), $op}">, DA;
"fcmove\t{$op, %st(0)|%ST(0), $op}">, DA;
def CMOVP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins),
"fcmovu {$op, %st(0)|%ST(0), $op}">, DA;
"fcmovu\t {$op, %st(0)|%ST(0), $op}">, DA;
def CMOVNB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins),
"fcmovnb {$op, %st(0)|%ST(0), $op}">, DB;
"fcmovnb\t{$op, %st(0)|%ST(0), $op}">, DB;
def CMOVNBE_F: FPI<0xD0, AddRegFrm, (outs RST:$op), (ins),
"fcmovnbe {$op, %st(0)|%ST(0), $op}">, DB;
"fcmovnbe\t{$op, %st(0)|%ST(0), $op}">, DB;
def CMOVNE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins),
"fcmovne {$op, %st(0)|%ST(0), $op}">, DB;
"fcmovne\t{$op, %st(0)|%ST(0), $op}">, DB;
def CMOVNP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins),
"fcmovnu {$op, %st(0)|%ST(0), $op}">, DB;
"fcmovnu\t{$op, %st(0)|%ST(0), $op}">, DB;
// Floating point loads & stores.
def LD_Fp32m : FpI<(outs RFP32:$dst), (ins f32mem:$src), ZeroArgFP,
@ -321,20 +321,20 @@ def IST_Fp16m64 : FpI<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, []>;
def IST_Fp32m64 : FpI<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, []>;
def IST_Fp64m64 : FpI<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, []>;
def LD_F32m : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s} $src">;
def LD_F64m : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld{l} $src">;
def ILD_F16m : FPI<0xDF, MRM0m, (outs), (ins i16mem:$src), "fild{s} $src">;
def ILD_F32m : FPI<0xDB, MRM0m, (outs), (ins i32mem:$src), "fild{l} $src">;
def ILD_F64m : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{ll} $src">;
def ST_F32m : FPI<0xD9, MRM2m, (outs), (ins f32mem:$dst), "fst{s} $dst">;
def ST_F64m : FPI<0xDD, MRM2m, (outs), (ins f64mem:$dst), "fst{l} $dst">;
def ST_FP32m : FPI<0xD9, MRM3m, (outs), (ins f32mem:$dst), "fstp{s} $dst">;
def ST_FP64m : FPI<0xDD, MRM3m, (outs), (ins f64mem:$dst), "fstp{l} $dst">;
def IST_F16m : FPI<0xDF, MRM2m, (outs), (ins i16mem:$dst), "fist{s} $dst">;
def IST_F32m : FPI<0xDB, MRM2m, (outs), (ins i32mem:$dst), "fist{l} $dst">;
def IST_FP16m : FPI<0xDF, MRM3m, (outs), (ins i16mem:$dst), "fistp{s} $dst">;
def IST_FP32m : FPI<0xDB, MRM3m, (outs), (ins i32mem:$dst), "fistp{l} $dst">;
def IST_FP64m : FPI<0xDF, MRM7m, (outs), (ins i64mem:$dst), "fistp{ll} $dst">;
def LD_F32m : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s}\t$src">;
def LD_F64m : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld{l}\t$src">;
def ILD_F16m : FPI<0xDF, MRM0m, (outs), (ins i16mem:$src), "fild{s}\t$src">;
def ILD_F32m : FPI<0xDB, MRM0m, (outs), (ins i32mem:$src), "fild{l}\t$src">;
def ILD_F64m : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{ll}\t$src">;
def ST_F32m : FPI<0xD9, MRM2m, (outs), (ins f32mem:$dst), "fst{s}\t$dst">;
def ST_F64m : FPI<0xDD, MRM2m, (outs), (ins f64mem:$dst), "fst{l}\t$dst">;
def ST_FP32m : FPI<0xD9, MRM3m, (outs), (ins f32mem:$dst), "fstp{s}\t$dst">;
def ST_FP64m : FPI<0xDD, MRM3m, (outs), (ins f64mem:$dst), "fstp{l}\t$dst">;
def IST_F16m : FPI<0xDF, MRM2m, (outs), (ins i16mem:$dst), "fist{s}\t$dst">;
def IST_F32m : FPI<0xDB, MRM2m, (outs), (ins i32mem:$dst), "fist{l}\t$dst">;
def IST_FP16m : FPI<0xDF, MRM3m, (outs), (ins i16mem:$dst), "fistp{s}\t$dst">;
def IST_FP32m : FPI<0xDB, MRM3m, (outs), (ins i32mem:$dst), "fistp{l}\t$dst">;
def IST_FP64m : FPI<0xDF, MRM7m, (outs), (ins i64mem:$dst), "fistp{ll}\t$dst">;
// FISTTP requires SSE3 even though it's a FPStack op.
def ISTT_Fp16m32 : FpI_<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP,
@ -356,15 +356,15 @@ def ISTT_Fp64m64 : FpI_<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP,
[(X86fp_to_i64mem RFP64:$src, addr:$op)]>,
Requires<[HasSSE3]>;
def ISTT_FP16m : FPI<0xDF, MRM1m, (outs), (ins i16mem:$dst), "fisttp{s} $dst">;
def ISTT_FP32m : FPI<0xDB, MRM1m, (outs), (ins i32mem:$dst), "fisttp{l} $dst">;
def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst), "fisttp{ll} $dst">;
def ISTT_FP16m : FPI<0xDF, MRM1m, (outs), (ins i16mem:$dst), "fisttp{s}\t$dst">;
def ISTT_FP32m : FPI<0xDB, MRM1m, (outs), (ins i32mem:$dst), "fisttp{l}\t$dst">;
def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst), "fisttp{ll}\t$dst">;
// FP Stack manipulation instructions.
def LD_Frr : FPI<0xC0, AddRegFrm, (outs), (ins RST:$op), "fld $op">, D9;
def ST_Frr : FPI<0xD0, AddRegFrm, (outs), (ins RST:$op), "fst $op">, DD;
def ST_FPrr : FPI<0xD8, AddRegFrm, (outs), (ins RST:$op), "fstp $op">, DD;
def XCH_F : FPI<0xC8, AddRegFrm, (outs), (ins RST:$op), "fxch $op">, D9;
def LD_Frr : FPI<0xC0, AddRegFrm, (outs), (ins RST:$op), "fld\t$op">, D9;
def ST_Frr : FPI<0xD0, AddRegFrm, (outs), (ins RST:$op), "fst\t$op">, DD;
def ST_FPrr : FPI<0xD8, AddRegFrm, (outs), (ins RST:$op), "fstp\t$op">, DD;
def XCH_F : FPI<0xC8, AddRegFrm, (outs), (ins RST:$op), "fxch\t$op">, D9;
// Floating point constant loads.
let isReMaterializable = 1 in {
@ -394,29 +394,29 @@ def UCOM_FpIr64: FpI<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
def UCOM_Fr : FPI<0xE0, AddRegFrm, // FPSW = cmp ST(0) with ST(i)
(outs), (ins RST:$reg),
"fucom $reg">, DD, Imp<[ST0],[]>;
"fucom\t$reg">, DD, Imp<[ST0],[]>;
def UCOM_FPr : FPI<0xE8, AddRegFrm, // FPSW = cmp ST(0) with ST(i), pop
(outs), (ins RST:$reg),
"fucomp $reg">, DD, Imp<[ST0],[]>;
"fucomp\t$reg">, DD, Imp<[ST0],[]>;
def UCOM_FPPr : FPI<0xE9, RawFrm, // cmp ST(0) with ST(1), pop, pop
(outs), (ins),
"fucompp">, DA, Imp<[ST0],[]>;
def UCOM_FIr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i)
(outs), (ins RST:$reg),
"fucomi {$reg, %st(0)|%ST(0), $reg}">, DB, Imp<[ST0],[]>;
"fucomi\t{$reg, %st(0)|%ST(0), $reg}">, DB, Imp<[ST0],[]>;
def UCOM_FIPr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i), pop
(outs), (ins RST:$reg),
"fucomip {$reg, %st(0)|%ST(0), $reg}">, DF, Imp<[ST0],[]>;
"fucomip\t{$reg, %st(0)|%ST(0), $reg}">, DF, Imp<[ST0],[]>;
// Floating point flag ops.
def FNSTSW8r : I<0xE0, RawFrm, // AX = fp flags
(outs), (ins), "fnstsw", []>, DF, Imp<[],[AX]>;
def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world
(outs), (ins i16mem:$dst), "fnstcw $dst", []>;
(outs), (ins i16mem:$dst), "fnstcw\t$dst", []>;
def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16]
(outs), (ins i16mem:$dst), "fldcw $dst", []>;
(outs), (ins i16mem:$dst), "fldcw\t$dst", []>;
//===----------------------------------------------------------------------===//
// Non-Instruction Patterns

974
lib/Target/X86/X86InstrInfo.td
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File diff suppressed because it is too large Load Diff

112
lib/Target/X86/X86InstrMMX.td
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@ -85,12 +85,12 @@ let isTwoAddress = 1 in {
multiclass MMXI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
ValueType OpVT, bit Commutable = 0> {
def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
!strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
[(set VR64:$dst, (OpVT (OpNode VR64:$src1, VR64:$src2)))]> {
let isCommutable = Commutable;
}
def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
!strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
[(set VR64:$dst, (OpVT (OpNode VR64:$src1,
(bitconvert
(load_mmx addr:$src2)))))]>;
@ -99,12 +99,12 @@ let isTwoAddress = 1 in {
multiclass MMXI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
bit Commutable = 0> {
def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
!strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
[(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]> {
let isCommutable = Commutable;
}
def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
!strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
[(set VR64:$dst, (IntId VR64:$src1,
(bitconvert (load_mmx addr:$src2))))]>;
}
@ -117,12 +117,12 @@ let isTwoAddress = 1 in {
multiclass MMXI_binop_rm_v1i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
bit Commutable = 0> {
def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
!strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
[(set VR64:$dst, (v1i64 (OpNode VR64:$src1, VR64:$src2)))]> {
let isCommutable = Commutable;
}
def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
!strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
[(set VR64:$dst,
(OpNode VR64:$src1,(load_mmx addr:$src2)))]>;
}
@ -130,14 +130,14 @@ let isTwoAddress = 1 in {
multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
string OpcodeStr, Intrinsic IntId> {
def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
!strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
[(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]>;
def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
!strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
[(set VR64:$dst, (IntId VR64:$src1,
(bitconvert (load_mmx addr:$src2))))]>;
def ri : MMXIi8<opc2, ImmForm, (outs VR64:$dst), (ins VR64:$src1, i32i8imm:$src2),
!strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
[(set VR64:$dst, (IntId VR64:$src1,
(scalar_to_vector (i32 imm:$src2))))]>;
}
@ -156,50 +156,50 @@ def MMX_FEMMS : MMXI<0x0E, RawFrm, (outs), (ins), "femms", [(int_x86_mmx_femms)]
// Data Transfer Instructions
def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
"movd {$src, $dst|$dst, $src}", []>;
"movd\t{$src, $dst|$dst, $src}", []>;
def MMX_MOVD64rm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src),
"movd {$src, $dst|$dst, $src}", []>;
"movd\t{$src, $dst|$dst, $src}", []>;
def MMX_MOVD64mr : MMXI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR64:$src),
"movd {$src, $dst|$dst, $src}", []>;
"movd\t{$src, $dst|$dst, $src}", []>;
def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
"movd {$src, $dst|$dst, $src}", []>;
"movd\t{$src, $dst|$dst, $src}", []>;
def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
"movq {$src, $dst|$dst, $src}", []>;
"movq\t{$src, $dst|$dst, $src}", []>;
def MMX_MOVQ64rm : MMXI<0x6F, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
"movq {$src, $dst|$dst, $src}",
"movq\t{$src, $dst|$dst, $src}",
[(set VR64:$dst, (load_mmx addr:$src))]>;
def MMX_MOVQ64mr : MMXI<0x7F, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
"movq {$src, $dst|$dst, $src}",
"movq\t{$src, $dst|$dst, $src}",
[(store (v1i64 VR64:$src), addr:$dst)]>;
def MMX_MOVDQ2Qrr : MMXID<0xD6, MRMDestMem, (outs VR64:$dst), (ins VR128:$src),
"movdq2q {$src, $dst|$dst, $src}",
"movdq2q\t{$src, $dst|$dst, $src}",
[(set VR64:$dst,
(v1i64 (vector_extract (v2i64 VR128:$src),
(iPTR 0))))]>;
def MMX_MOVQ2DQrr : MMXIS<0xD6, MRMDestMem, (outs VR128:$dst), (ins VR64:$src),
"movq2dq {$src, $dst|$dst, $src}",
"movq2dq\t{$src, $dst|$dst, $src}",
[(set VR128:$dst,
(bitconvert (v1i64 VR64:$src)))]>;
def MMX_MOVNTQmr : MMXI<0xE7, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
"movntq {$src, $dst|$dst, $src}",
"movntq\t{$src, $dst|$dst, $src}",
[(int_x86_mmx_movnt_dq addr:$dst, VR64:$src)]>;
let AddedComplexity = 15 in
// movd to MMX register zero-extends
def MMX_MOVZDI2PDIrr : MMX2I<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
"movd {$src, $dst|$dst, $src}",
"movd\t{$src, $dst|$dst, $src}",
[(set VR64:$dst,
(v2i32 (vector_shuffle immAllZerosV,
(v2i32 (scalar_to_vector GR32:$src)),
MMX_MOVL_shuffle_mask)))]>;
let AddedComplexity = 20 in
def MMX_MOVZDI2PDIrm : MMX2I<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src),
"movd {$src, $dst|$dst, $src}",
"movd\t{$src, $dst|$dst, $src}",
[(set VR64:$dst,
(v2i32 (vector_shuffle immAllZerosV,
(v2i32 (scalar_to_vector
@ -261,12 +261,12 @@ defm MMX_PXOR : MMXI_binop_rm_v1i64<0xEF, "pxor", xor, 1>;
let isTwoAddress = 1 in {
def MMX_PANDNrr : MMXI<0xDF, MRMSrcReg,
(outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
"pandn {$src2, $dst|$dst, $src2}",
"pandn\t{$src2, $dst|$dst, $src2}",
[(set VR64:$dst, (v1i64 (and (vnot VR64:$src1),
VR64:$src2)))]>;
def MMX_PANDNrm : MMXI<0xDF, MRMSrcMem,
(outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
"pandn {$src2, $dst|$dst, $src2}",
"pandn\t{$src2, $dst|$dst, $src2}",
[(set VR64:$dst, (v1i64 (and (vnot VR64:$src1),
(load addr:$src2))))]>;
}
@ -307,13 +307,13 @@ let isTwoAddress = 1 in {
// Unpack High Packed Data Instructions
def MMX_PUNPCKHBWrr : MMXI<0x68, MRMSrcReg,
(outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
"punpckhbw {$src2, $dst|$dst, $src2}",
"punpckhbw\t{$src2, $dst|$dst, $src2}",
[(set VR64:$dst,
(v8i8 (vector_shuffle VR64:$src1, VR64:$src2,
MMX_UNPCKH_shuffle_mask)))]>;
def MMX_PUNPCKHBWrm : MMXI<0x68, MRMSrcMem,
(outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
"punpckhbw {$src2, $dst|$dst, $src2}",
"punpckhbw\t{$src2, $dst|$dst, $src2}",
[(set VR64:$dst,
(v8i8 (vector_shuffle VR64:$src1,
(bc_v8i8 (load_mmx addr:$src2)),
@ -321,13 +321,13 @@ let isTwoAddress = 1 in {
def MMX_PUNPCKHWDrr : MMXI<0x69, MRMSrcReg,
(outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
"punpckhwd {$src2, $dst|$dst, $src2}",
"punpckhwd\t{$src2, $dst|$dst, $src2}",
[(set VR64:$dst,
(v4i16 (vector_shuffle VR64:$src1, VR64:$src2,
MMX_UNPCKH_shuffle_mask)))]>;
def MMX_PUNPCKHWDrm : MMXI<0x69, MRMSrcMem,
(outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
"punpckhwd {$src2, $dst|$dst, $src2}",
"punpckhwd\t{$src2, $dst|$dst, $src2}",
[(set VR64:$dst,
(v4i16 (vector_shuffle VR64:$src1,
(bc_v4i16 (load_mmx addr:$src2)),
@ -335,13 +335,13 @@ let isTwoAddress = 1 in {
def MMX_PUNPCKHDQrr : MMXI<0x6A, MRMSrcReg,
(outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
"punpckhdq {$src2, $dst|$dst, $src2}",
"punpckhdq\t{$src2, $dst|$dst, $src2}",
[(set VR64:$dst,
(v2i32 (vector_shuffle VR64:$src1, VR64:$src2,
MMX_UNPCKH_shuffle_mask)))]>;
def MMX_PUNPCKHDQrm : MMXI<0x6A, MRMSrcMem,
(outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
"punpckhdq {$src2, $dst|$dst, $src2}",
"punpckhdq\t{$src2, $dst|$dst, $src2}",
[(set VR64:$dst,
(v2i32 (vector_shuffle VR64:$src1,
(bc_v2i32 (load_mmx addr:$src2)),
@ -350,13 +350,13 @@ let isTwoAddress = 1 in {
// Unpack Low Packed Data Instructions
def MMX_PUNPCKLBWrr : MMXI<0x60, MRMSrcReg,
(outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
"punpcklbw {$src2, $dst|$dst, $src2}",
"punpcklbw\t{$src2, $dst|$dst, $src2}",
[(set VR64:$dst,
(v8i8 (vector_shuffle VR64:$src1, VR64:$src2,
MMX_UNPCKL_shuffle_mask)))]>;
def MMX_PUNPCKLBWrm : MMXI<0x60, MRMSrcMem,
(outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
"punpcklbw {$src2, $dst|$dst, $src2}",
"punpcklbw\t{$src2, $dst|$dst, $src2}",
[(set VR64:$dst,
(v8i8 (vector_shuffle VR64:$src1,
(bc_v8i8 (load_mmx addr:$src2)),
@ -364,13 +364,13 @@ let isTwoAddress = 1 in {
def MMX_PUNPCKLWDrr : MMXI<0x61, MRMSrcReg,
(outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
"punpcklwd {$src2, $dst|$dst, $src2}",
"punpcklwd\t{$src2, $dst|$dst, $src2}",
[(set VR64:$dst,
(v4i16 (vector_shuffle VR64:$src1, VR64:$src2,
MMX_UNPCKL_shuffle_mask)))]>;
def MMX_PUNPCKLWDrm : MMXI<0x61, MRMSrcMem,
(outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
"punpcklwd {$src2, $dst|$dst, $src2}",
"punpcklwd\t{$src2, $dst|$dst, $src2}",
[(set VR64:$dst,
(v4i16 (vector_shuffle VR64:$src1,
(bc_v4i16 (load_mmx addr:$src2)),
@ -378,13 +378,13 @@ let isTwoAddress = 1 in {
def MMX_PUNPCKLDQrr : MMXI<0x62, MRMSrcReg,
(outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
"punpckldq {$src2, $dst|$dst, $src2}",
"punpckldq\t{$src2, $dst|$dst, $src2}",
[(set VR64:$dst,
(v2i32 (vector_shuffle VR64:$src1, VR64:$src2,
MMX_UNPCKL_shuffle_mask)))]>;
def MMX_PUNPCKLDQrm : MMXI<0x62, MRMSrcMem,
(outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
"punpckldq {$src2, $dst|$dst, $src2}",
"punpckldq\t{$src2, $dst|$dst, $src2}",
[(set VR64:$dst,
(v2i32 (vector_shuffle VR64:$src1,
(bc_v2i32 (load_mmx addr:$src2)),
@ -399,14 +399,14 @@ defm MMX_PACKUSWB : MMXI_binop_rm_int<0x67, "packuswb", int_x86_mmx_packuswb>;
// -- Shuffle Instructions
def MMX_PSHUFWri : MMXIi8<0x70, MRMSrcReg,
(outs VR64:$dst), (ins VR64:$src1, i8imm:$src2),
"pshufw {$src2, $src1, $dst|$dst, $src1, $src2}",
"pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
[(set VR64:$dst,
(v4i16 (vector_shuffle
VR64:$src1, (undef),
MMX_PSHUFW_shuffle_mask:$src2)))]>;
def MMX_PSHUFWmi : MMXIi8<0x70, MRMSrcMem,
(outs VR64:$dst), (ins i64mem:$src1, i8imm:$src2),
"pshufw {$src2, $src1, $dst|$dst, $src1, $src2}",
"pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
[(set VR64:$dst,
(v4i16 (vector_shuffle
(bc_v4i16 (load_mmx addr:$src1)),
@ -415,34 +415,34 @@ def MMX_PSHUFWmi : MMXIi8<0x70, MRMSrcMem,
// -- Conversion Instructions
def MMX_CVTPD2PIrr : MMX2I<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
"cvtpd2pi {$src, $dst|$dst, $src}", []>;
"cvtpd2pi\t{$src, $dst|$dst, $src}", []>;
def MMX_CVTPD2PIrm : MMX2I<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
"cvtpd2pi {$src, $dst|$dst, $src}", []>;
"cvtpd2pi\t{$src, $dst|$dst, $src}", []>;
def MMX_CVTPI2PDrr : MMX2I<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
"cvtpi2pd {$src, $dst|$dst, $src}", []>;
"cvtpi2pd\t{$src, $dst|$dst, $src}", []>;
def MMX_CVTPI2PDrm : MMX2I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
"cvtpi2pd {$src, $dst|$dst, $src}", []>;
"cvtpi2pd\t{$src, $dst|$dst, $src}", []>;
def MMX_CVTPI2PSrr : MMXI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
"cvtpi2ps {$src, $dst|$dst, $src}", []>;
"cvtpi2ps\t{$src, $dst|$dst, $src}", []>;
def MMX_CVTPI2PSrm : MMXI<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
"cvtpi2ps {$src, $dst|$dst, $src}", []>;
"cvtpi2ps\t{$src, $dst|$dst, $src}", []>;
def MMX_CVTPS2PIrr : MMXI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
"cvtps2pi {$src, $dst|$dst, $src}", []>;
"cvtps2pi\t{$src, $dst|$dst, $src}", []>;
def MMX_CVTPS2PIrm : MMXI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
"cvtps2pi {$src, $dst|$dst, $src}", []>;
"cvtps2pi\t{$src, $dst|$dst, $src}", []>;
def MMX_CVTTPD2PIrr : MMX2I<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
"cvttpd2pi {$src, $dst|$dst, $src}", []>;
"cvttpd2pi\t{$src, $dst|$dst, $src}", []>;
def MMX_CVTTPD2PIrm : MMX2I<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
"cvttpd2pi {$src, $dst|$dst, $src}", []>;
"cvttpd2pi\t{$src, $dst|$dst, $src}", []>;
def MMX_CVTTPS2PIrr : MMXI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
"cvttps2pi {$src, $dst|$dst, $src}", []>;
"cvttps2pi\t{$src, $dst|$dst, $src}", []>;
def MMX_CVTTPS2PIrm : MMXI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
"cvttps2pi {$src, $dst|$dst, $src}", []>;
"cvttps2pi\t{$src, $dst|$dst, $src}", []>;
// Extract / Insert
def MMX_X86pextrw : SDNode<"X86ISD::PEXTRW", SDTypeProfile<1, 2, []>, []>;
@ -450,18 +450,18 @@ def MMX_X86pinsrw : SDNode<"X86ISD::PINSRW", SDTypeProfile<1, 3, []>, []>;
def MMX_PEXTRWri : MMXIi8<0xC5, MRMSrcReg,
(outs GR32:$dst), (ins VR64:$src1, i16i8imm:$src2),
"pextrw {$src2, $src1, $dst|$dst, $src1, $src2}",
"pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
[(set GR32:$dst, (MMX_X86pextrw (v4i16 VR64:$src1),
(iPTR imm:$src2)))]>;
let isTwoAddress = 1 in {
def MMX_PINSRWrri : MMXIi8<0xC4, MRMSrcReg,
(outs VR64:$dst), (ins VR64:$src1, GR32:$src2, i16i8imm:$src3),
"pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
"pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
[(set VR64:$dst, (v4i16 (MMX_X86pinsrw (v4i16 VR64:$src1),
GR32:$src2, (iPTR imm:$src3))))]>;
def MMX_PINSRWrmi : MMXIi8<0xC4, MRMSrcMem,
(outs VR64:$dst), (ins VR64:$src1, i16mem:$src2, i16i8imm:$src3),
"pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
"pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
[(set VR64:$dst,
(v4i16 (MMX_X86pinsrw (v4i16 VR64:$src1),
(i32 (anyext (loadi16 addr:$src2))),
@ -470,12 +470,12 @@ let isTwoAddress = 1 in {
// Mask creation
def MMX_PMOVMSKBrr : MMXI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR64:$src),
"pmovmskb {$src, $dst|$dst, $src}",
"pmovmskb\t{$src, $dst|$dst, $src}",
[(set GR32:$dst, (int_x86_mmx_pmovmskb VR64:$src))]>;
// Misc.
def MMX_MASKMOVQ : MMXI<0xF7, MRMDestMem, (outs), (ins VR64:$src, VR64:$mask),
"maskmovq {$mask, $src|$src, $mask}",
"maskmovq\t{$mask, $src|$src, $mask}",
[(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, EDI)]>,
Imp<[EDI],[]>;
@ -487,10 +487,10 @@ def MMX_MASKMOVQ : MMXI<0xF7, MRMDestMem, (outs), (ins VR64:$src, VR64:$mask),
// FIXME: remove when we can teach regalloc that xor reg, reg is ok.
let isReMaterializable = 1 in {
def MMX_V_SET0 : MMXI<0xEF, MRMInitReg, (outs VR64:$dst), (ins),
"pxor $dst, $dst",
"pxor\t$dst, $dst",
[(set VR64:$dst, (v1i64 immAllZerosV))]>;
def MMX_V_SETALLONES : MMXI<0x76, MRMInitReg, (outs VR64:$dst), (ins),
"pcmpeqd $dst, $dst",
"pcmpeqd\t$dst, $dst",
[(set VR64:$dst, (v1i64 immAllOnesV))]>;
}

604
lib/Target/X86/X86InstrSSE.td
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File diff suppressed because it is too large Load Diff

430
lib/Target/X86/X86InstrX86-64.td
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File diff suppressed because it is too large Load Diff

2
test/CodeGen/Generic/2007-02-23-DAGCombine-Miscompile.ll
View File

@ -1,5 +1,5 @@
; PR1219
; RUN: llvm-as < %s | llc -march=x86 | grep {movl \$1, %eax}
; RUN: llvm-as < %s | llc -march=x86 | grep {movl \$1, %eax}
define i32 @test(i1 %X) {
old_entry1:

2
test/CodeGen/Generic/phi-immediate-factoring.ll
View File

@ -1,5 +1,5 @@
; PR1296
; RUN: llvm-as < %s | llc -march=x86 | grep {movl \$1} | wc -l | grep 1
; RUN: llvm-as < %s | llc -march=x86 | grep {movl \$1} | wc -l | grep 1
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
target triple = "i686-apple-darwin8"

2
test/CodeGen/X86/2006-04-27-ISelFoldingBug.ll
View File

@ -1,6 +1,6 @@
; RUN: llvm-upgrade < %s | llvm-as | \
; RUN: llc -march=x86 -mtriple=i686-apple-darwin8 -relocation-model=static | \
; RUN: grep {movl _last} | wc -l | grep 1
; RUN: grep {movl _last} | wc -l | grep 1
; RUN: llvm-upgrade < %s | llvm-as | \
; RUN: llc -march=x86 -mtriple=i686-apple-darwin8 -relocation-model=static | \
; RUN: grep {cmpl.*_last} | wc -l | grep 1

2
test/CodeGen/X86/2006-11-12-CSRetCC.ll
View File

@ -1,4 +1,4 @@
; RUN: llvm-upgrade < %s | llvm-as | llc -march=x86 | grep {subl \$4, %esp}
; RUN: llvm-upgrade < %s | llvm-as | llc -march=x86 | grep {subl \$4, %esp}
target triple = "i686-pc-linux-gnu"

4
test/CodeGen/X86/2006-11-17-IllegalMove.ll
View File

@ -1,7 +1,7 @@
; RUN: llvm-upgrade < %s | llvm-as | llc -march=x86-64 | \
; RUN: not grep {movb %sil, %ah}
; RUN: not grep {movb %sil, %ah}
; RUN: llvm-upgrade < %s | llvm-as | llc -march=x86-64 | \
; RUN: grep {movzbw %al, %ax}
; RUN: grep {movzbw %al, %ax}
void %handle_vector_size_attribute() {
entry:

2
test/CodeGen/X86/2006-11-28-Memcpy.ll
View File

@ -2,7 +2,7 @@
; RUN: llvm-upgrade < %s | llvm-as | llc -march=x86 | \
; RUN: grep 3721182122 | wc -l | grep 2
; RUN: llvm-upgrade < %s | llvm-as | llc -march=x86 | \
; RUN: grep -E {movl _?bytes2} | wc -l | grep 1
; RUN: grep -E {movl _?bytes2} | wc -l | grep 1
%fmt = constant [4 x sbyte] c"%x\0A\00"
%bytes = constant [4 x sbyte] c"\AA\BB\CC\DD"

2
test/CodeGen/X86/2007-01-08-InstrSched.ll
View File

@ -1,6 +1,6 @@
; PR1075
; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin | \
; RUN: %prcontext {mulss LCPI1_3} 1 | grep mulss | wc -l | grep 1
; RUN: %prcontext {mulss LCPI1_3} 1 | grep mulss | wc -l | grep 1
define float @foo(float %x) {
%tmp1 = mul float %x, 3.000000e+00

4
test/CodeGen/X86/2007-02-04-OrAddrMode.ll
View File

@ -1,5 +1,5 @@
; RUN: llvm-as < %s | llc -march=x86 | grep {orl \$1, %eax}
; RUN: llvm-as < %s | llc -march=x86 | grep {leal 3(,%eax,8)}
; RUN: llvm-as < %s | llc -march=x86 | grep {orl \$1, %eax}
; RUN: llvm-as < %s | llc -march=x86 | grep {leal 3(,%eax,8)}
;; This example can't fold the or into an LEA.
define i32 @test(float ** %tmp2, i32 %tmp12) {

6
test/CodeGen/X86/2007-07-03-GR64ToVR64.ll
View File

@ -1,6 +1,6 @@
; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+mmx | grep {movd %rsi, %mm0} &&
; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+mmx | grep {movd %rdi, %mm1} &&
; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+mmx | grep {paddusw %mm0, %mm1}
; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+mmx | grep {movd %rsi, %mm0} &&
; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+mmx | grep {movd %rdi, %mm1} &&
; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+mmx | grep {paddusw %mm0, %mm1}
@R = external global <1 x i64> ; <<1 x i64>*> [#uses=1]

4
test/CodeGen/X86/2007-07-18-Vector-Extract.ll
View File

@ -1,5 +1,5 @@
; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+sse | grep {movq (%rdi), %rax}
; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+sse | grep {movq 8(%rdi), %rax}
; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+sse | grep {movq (%rdi), %rax}
; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+sse | grep {movq 8(%rdi), %rax}
define i64 @foo_0(<2 x i64>* %val) {
entry:
%val12 = getelementptr <2 x i64>* %val, i32 0, i32 0 ; <i64*> [#uses=1]

2
test/CodeGen/X86/commute-two-addr.ll
View File

@ -3,7 +3,7 @@
; Make sure there are only 3 mov's for each testcase
; RUN: llvm-upgrade < %s | llvm-as | llc -march=x86 -x86-asm-syntax=intel | \
; RUN: grep {mov } | wc -l | grep 6
; RUN: grep {\\\<mov\\\>} | wc -l | grep 6
target triple = "i686-pc-linux-gnu"

2
test/CodeGen/X86/epilogue.ll
View File

@ -1,5 +1,5 @@
; RUN: llvm-as < %s | llc -march=x86 | not grep lea
; RUN: llvm-as < %s | llc -march=x86 | grep {movl %ebp}
; RUN: llvm-as < %s | llc -march=x86 | grep {movl %ebp}
declare void @bar(<2 x i64>* %n)

2
test/CodeGen/X86/fast-cc-callee-pops.ll
View File

@ -1,5 +1,5 @@
; RUN: llvm-upgrade < %s | llvm-as | \
; RUN: llc -march=x86 -x86-asm-syntax=intel -mcpu=yonah | grep {ret 20}
; RUN: llc -march=x86 -x86-asm-syntax=intel -mcpu=yonah | grep {ret 20}
; Check that a fastcc function pops its stack variables before returning.

2
test/CodeGen/X86/fast-cc-merge-stack-adj.ll
View File

@ -1,5 +1,5 @@
; RUN: llvm-upgrade < %s | llvm-as | llc -march=x86 -x86-asm-syntax=intel | \
; RUN: grep {add ESP, 8}
; RUN: grep {add ESP, 8}
target triple = "i686-pc-linux-gnu"

2
test/CodeGen/X86/fast-cc-pass-in-regs.ll
View File

@ -1,5 +1,5 @@
; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel | \
; RUN: grep {mov EDX, 1}
; RUN: grep {mov EDX, 1}
; check that fastcc is passing stuff in regs.
declare x86_fastcallcc i64 @callee(i64)

4
test/CodeGen/X86/i128-ret.ll
View File

@ -1,5 +1,5 @@
; RUN: llvm-as < %s | llc -march=x86-64 | grep {movq 8(%rdi), %rdx}
; RUN: llvm-as < %s | llc -march=x86-64 | grep {movq (%rdi), %rax}
; RUN: llvm-as < %s | llc -march=x86-64 | grep {movq 8(%rdi), %rdx}
; RUN: llvm-as < %s | llc -march=x86-64 | grep {movq (%rdi), %rax}
define i128 @test(i128 *%P) {
%A = load i128* %P

8
test/CodeGen/X86/illegal-vector-args-return.ll
View File

@ -1,7 +1,7 @@
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep {mulpd %xmm3, %xmm1}
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep {mulpd %xmm2, %xmm0}
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep {addps %xmm3, %xmm1}
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep {addps %xmm2, %xmm0}
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep {mulpd %xmm3, %xmm1}
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep {mulpd %xmm2, %xmm0}
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep {addps %xmm3, %xmm1}
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep {addps %xmm2, %xmm0}
define <4 x double> @foo(<4 x double> %x, <4 x double> %z) {
%y = mul <4 x double> %x, %z

2
test/CodeGen/X86/isel-sink.ll
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@ -1,6 +1,6 @@
; RUN: llvm-as < %s | llc -march=x86 | not grep lea
; RUN: llvm-as < %s | llc -march=x86 -mtriple=i686-apple-darwin8 | \
; RUN: grep {movl \$4, (.*,.*,4)}
; RUN: grep {movl \$4, (.*,.*,4)}
define i32 @test(i32* %X, i32 %B) {
; This gep should be sunk out of this block into the load/store users.

2
test/CodeGen/X86/lea-2.ll
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@ -1,5 +1,5 @@
; RUN: llvm-upgrade < %s | llvm-as | llc -march=x86 -x86-asm-syntax=intel | \
; RUN: grep {lea EAX, DWORD PTR \\\[... + 4\\*... - 5\\\]}
; RUN: grep {lea EAX, DWORD PTR \\\[... + 4\\*... - 5\\\]}
; RUN: llvm-upgrade < %s | llvm-as | llc -march=x86 -x86-asm-syntax=intel | \
; RUN: not grep add

4
test/CodeGen/X86/lea-3.ll
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@ -1,11 +1,11 @@
; RUN: llvm-as < %s | llc -march=x86-64 | grep {leal (%rdi,%rdi,2), %eax}
; RUN: llvm-as < %s | llc -march=x86-64 | grep {leal (%rdi,%rdi,2), %eax}
define i32 @test(i32 %a) {
%tmp2 = mul i32 %a, 3 ; <i32> [#uses=1]
ret i32 %tmp2
}
; RUN: llvm-as < %s | llc -march=x86-64 | grep {leaq (,%rdi,4), %rax}
; RUN: llvm-as < %s | llc -march=x86-64 | grep {leaq (,%rdi,4), %rax}
define i64 @test2(i64 %a) {
%tmp2 = shl i64 %a, 2
%tmp3 = or i64 %tmp2, %a

2
test/CodeGen/X86/mingw-alloca.ll
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@ -1,7 +1,7 @@
; RUN: llvm-as < %s | llc -o %t -f
; RUN: grep __alloca %t | wc -l | grep 2
; RUN: grep 8028 %t
; RUN: grep {pushl %eax} %t
; RUN: grep {pushl %eax} %t
; RUN: grep 8024 %t | wc -l | grep 2
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"

2
test/CodeGen/X86/peep-vector-extract-concat.ll
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@ -1,4 +1,4 @@
; RUN: llvm-as < %s | llc -march=x86-64 | grep {shufps \$3, %xmm0, %xmm0}
; RUN: llvm-as < %s | llc -march=x86-64 | grep {shufps \$3, %xmm0, %xmm0}
define float @foo(<8 x float> %a) {
%c = extractelement <8 x float> %a, i32 3

2
test/CodeGen/X86/peep-vector-extract-insert.ll
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@ -1,4 +1,4 @@
; RUN: llvm-as < %s | llc -march=x86-64 | grep {pxor %xmm0, %xmm0} | wc -l | grep 2
; RUN: llvm-as < %s | llc -march=x86-64 | grep {pxor %xmm0, %xmm0} | wc -l | grep 2
define float @foo(<4 x float> %a) {
%b = insertelement <4 x float> %a, float 0.0, i32 3

2
test/CodeGen/X86/shift-codegen.ll
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@ -1,5 +1,5 @@
; RUN: llvm-as < %s | llc -relocation-model=static -march=x86 | \
; RUN: grep {shll \$3} | wc -l | grep 2
; RUN: grep {shll \$3} | wc -l | grep 2
; This should produce two shll instructions, not any lea's.

6
test/CodeGen/X86/shl_elim.ll
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@ -1,6 +1,6 @@
; RUN: llvm-as < %s | llc -march=x86 | grep {movl 8(.esp), %eax}
; RUN: llvm-as < %s | llc -march=x86 | grep {shll .15, .eax}
; RUN: llvm-as < %s | llc -march=x86 | grep {sarl .16, .eax}
; RUN: llvm-as < %s | llc -march=x86 | grep {movl 8(.esp), %eax}
; RUN: llvm-as < %s | llc -march=x86 | grep {shll .15, .eax}
; RUN: llvm-as < %s | llc -march=x86 | grep {sarl .16, .eax}
define i32 @test1(i64 %a) {
%tmp29 = lshr i64 %a, 24 ; <i64> [#uses=1]

2
test/CodeGen/X86/store_op_load_fold2.ll
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@ -1,5 +1,5 @@
; RUN: llvm-upgrade < %s | llvm-as | llc -march=x86 -x86-asm-syntax=intel | \
; RUN: grep {and DWORD PTR} | wc -l | grep 2
; RUN: grep {and DWORD PTR} | wc -l | grep 2
target endian = little
target pointersize = 32

6
test/CodeGen/X86/tls1.ll
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@ -1,9 +1,9 @@
; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu | \
; RUN: grep {movl %gs:i@NTPOFF, %eax}
; RUN: grep {movl %gs:i@NTPOFF, %eax}
; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu | \
; RUN: grep {leal i@NTPOFF(%eax), %eax}
; RUN: grep {leal i@NTPOFF(%eax), %eax}
; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu -relocation-model=pic | \
; RUN: grep {leal i@TLSGD(,%ebx,1), %eax}
; RUN: grep {leal i@TLSGD(,%ebx,1), %eax}
@i = thread_local global i32 15 ; <i32*> [#uses=2]

6
test/CodeGen/X86/tls2.ll
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@ -1,9 +1,9 @@
; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu | \
; RUN: grep {movl %gs:(%eax), %eax}
; RUN: grep {movl %gs:(%eax), %eax}
; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu | \
; RUN: grep {addl i@INDNTPOFF, %eax}
; RUN: grep {addl i@INDNTPOFF, %eax}
; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu -relocation-model=pic | \
; RUN: grep {leal i@TLSGD(,%ebx,1), %eax}
; RUN: grep {leal i@TLSGD(,%ebx,1), %eax}
@i = external thread_local global i32 ; <i32*> [#uses=2]

2
test/CodeGen/X86/x86-64-arg.ll
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@ -1,4 +1,4 @@
; RUN: llvm-as < %s | llc | grep {movl %edi, %eax}
; RUN: llvm-as < %s | llc | grep {movl %edi, %eax}
; The input value is already sign extended, don't re-extend it.
; This testcase corresponds to:
; int test(short X) { return (int)X; }

2
test/Transforms/TailDup/if-tail-dup.ll
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@ -1,6 +1,6 @@
; RUN: llvm-upgrade < %s | llvm-as | opt -tailduplicate | \
; RUN: llc -march=x86 -o %t -f
; RUN: grep {je } %t
; RUN: grep {\\\<je\\\>} %t
; RUN: not grep jmp %t
; END.
; This should have no unconditional jumps in it. The C source is: