RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 19:23:23 +01:00
Code Issues Projects Releases Wiki Activity

[ARMv8] Add some missing tests for DSB/DMB.

Browse Source 
llvm-svn: 190060
This commit is contained in:
Joey Gouly 2013-09-05 16:05:45 +00:00
parent 071ca2ff6d
commit e37f727df1
3 changed files with 57 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

37
test/MC/ARM/basic-thumb2-instructions-v8.s
View File

@ -1,6 +1,6 @@
@ New ARMv8 T32 encodings
@ RUN: llvm-mc -triple thumbv8 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-V8
@ RUN: not llvm-mc -triple thumbv8 -show-encoding -mattr=+db < %s | FileCheck %s --check-prefix=CHECK-V8
@ RUN: not llvm-mc -triple thumbv7 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V7
@ HLT
@ -34,3 +34,38 @@
@ CHECK-V7: error: instruction requires: armv8
@ CHECK-V7: error: instruction requires: armv8
@ CHECK-V7: error: instruction requires: armv8
@------------------------------------------------------------------------------
@ DMB (v8 barriers)
@------------------------------------------------------------------------------
dmb ishld
dmb oshld
dmb nshld
dmb ld
dmb #20
@ CHECK-V8: dmb ishld @ encoding: [0xbf,0xf3,0x59,0x8f]
@ CHECK-V8: dmb oshld @ encoding: [0xbf,0xf3,0x51,0x8f]
@ CHECK-V8: dmb nshld @ encoding: [0xbf,0xf3,0x55,0x8f]
@ CHECK-V8: dmb ld @ encoding: [0xbf,0xf3,0x5d,0x8f]
@ CHECK-V7: error: invalid operand for instruction
@ CHECK-V7: error: invalid operand for instruction
@ CHECK-V7: error: invalid operand for instruction
@ CHECK-V7: error: invalid operand for instruction
@ CHECK-V7: error: immediate value out of range
@------------------------------------------------------------------------------
@ DSB (v8 barriers)
@------------------------------------------------------------------------------
dsb ishld
dsb oshld
dsb nshld
dsb ld
@ CHECK-V8: dsb ishld @ encoding: [0xbf,0xf3,0x49,0x8f]
@ CHECK-V8: dsb oshld @ encoding: [0xbf,0xf3,0x41,0x8f]
@ CHECK-V8: dsb nshld @ encoding: [0xbf,0xf3,0x45,0x8f]
@ CHECK-V8: dsb ld @ encoding: [0xbf,0xf3,0x4d,0x8f]
@ CHECK-V7: error: invalid operand for instruction
@ CHECK-V7: error: invalid operand for instruction
@ CHECK-V7: error: invalid operand for instruction

11
test/MC/Disassembler/ARM/basic-arm-instructions-v8.txt
View File

@ -1,4 +1,4 @@
# RUN: llvm-mc -disassemble -triple armv8 -show-encoding < %s | FileCheck %s
# RUN: llvm-mc -disassemble -triple armv8 -mattr=+db -show-encoding < %s | FileCheck %s
# New v8 ARM instructions
@ -9,3 +9,12 @@
0x7f 0xff 0x0f 0xe1
# CHECK: hlt #65535
0x59 0xf0 0x7f 0xf5
0x51 0xf0 0x7f 0xf5
0x55 0xf0 0x7f 0xf5
0x5d 0xf0 0x7f 0xf5
# CHECK: dmb ishld
# CHECK: dmb oshld
# CHECK: dmb nshld
# CHECK: dmb ld

12
test/MC/Disassembler/ARM/thumb-v8.txt
View File

@ -1,4 +1,4 @@
# RUN: llvm-mc -disassemble -triple thumbv8 -show-encoding < %s | FileCheck %s
# RUN: llvm-mc -disassemble -triple thumbv8 -mattr=+db -show-encoding < %s | FileCheck %s
0x80 0xba
# CHECK: hlt #0
@ -16,3 +16,13 @@
0x8f 0xf7 0x03 0x80
# CHECK: dcps3
0xbf 0xf3 0x59 0x8f
0xbf 0xf3 0x51 0x8f
0xbf 0xf3 0x55 0x8f
0xbf 0xf3 0x5d 0x8f
# CHECK: dmb ishld
# CHECK: dmb oshld
# CHECK: dmb nshld
# CHECK: dmb ld