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Implement some relaxations for arithmetic instructions. The limitation
on RIP relative relocations looks artificial, but this is a superset of what we were able to do before. llvm-svn: 117364
This commit is contained in:
Rafael Espindola
parent
5e0c84786b
commit
e38790534e
@ -69,16 +69,11 @@ public:
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};
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};
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} // end anonymous namespace
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} // end anonymous namespace
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static unsigned getRelaxedOpcode(unsigned Op) {
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static unsigned getRelaxedOpcodeBranch(unsigned Op) {
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switch (Op) {
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switch (Op) {
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default:
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default:
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return Op;
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return Op;
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// This is used on i386 with things like addl $foo, %ebx
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// FIXME: Should the other *i8 instructions be here too? If not, it might
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// be better to just select X86::ADD32ri instead of X86::ADD32ri8.
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case X86::ADD32ri8: return X86::ADD32ri;
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case X86::JAE_1: return X86::JAE_4;
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case X86::JAE_1: return X86::JAE_4;
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case X86::JA_1: return X86::JA_4;
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case X86::JA_1: return X86::JA_4;
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case X86::JBE_1: return X86::JBE_4;
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case X86::JBE_1: return X86::JBE_4;
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@ -99,16 +94,101 @@ static unsigned getRelaxedOpcode(unsigned Op) {
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}
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}
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}
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}
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static unsigned getRelaxedOpcodeArith(unsigned Op) {
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switch (Op) {
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default:
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return Op;
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// IMUL
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case X86::IMUL16rri8: return X86::IMUL16rri;
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case X86::IMUL16rmi8: return X86::IMUL16rmi;
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case X86::IMUL32rri8: return X86::IMUL32rri;
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case X86::IMUL32rmi8: return X86::IMUL32rmi;
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case X86::IMUL64rri8: return X86::IMUL64rri32;
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case X86::IMUL64rmi8: return X86::IMUL64rmi32;
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// AND
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case X86::AND16ri8: return X86::AND16ri;
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case X86::AND16mi8: return X86::AND16mi;
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case X86::AND32ri8: return X86::AND32ri;
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case X86::AND32mi8: return X86::AND32mi;
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case X86::AND64ri8: return X86::AND64ri32;
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case X86::AND64mi8: return X86::AND64mi32;
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// OR
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case X86::OR16ri8: return X86::OR16ri;
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case X86::OR16mi8: return X86::OR16mi;
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case X86::OR32ri8: return X86::OR32ri;
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case X86::OR32mi8: return X86::OR32mi;
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case X86::OR64ri8: return X86::OR64ri32;
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case X86::OR64mi8: return X86::OR64mi32;
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// XOR
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case X86::XOR16ri8: return X86::XOR16ri;
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case X86::XOR16mi8: return X86::XOR16mi;
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case X86::XOR32ri8: return X86::XOR32ri;
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case X86::XOR32mi8: return X86::XOR32mi;
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case X86::XOR64ri8: return X86::XOR64ri32;
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case X86::XOR64mi8: return X86::XOR64mi32;
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// ADD
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case X86::ADD16ri8: return X86::ADD16ri;
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case X86::ADD16mi8: return X86::ADD16mi;
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case X86::ADD32ri8: return X86::ADD32ri;
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case X86::ADD32mi8: return X86::ADD32mi;
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case X86::ADD64ri8: return X86::ADD64ri32;
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case X86::ADD64mi8: return X86::ADD64mi32;
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// SUB
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case X86::SUB16ri8: return X86::SUB16ri;
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case X86::SUB16mi8: return X86::SUB16mi;
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case X86::SUB32ri8: return X86::SUB32ri;
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case X86::SUB32mi8: return X86::SUB32mi;
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case X86::SUB64ri8: return X86::SUB64ri32;
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case X86::SUB64mi8: return X86::SUB64mi32;
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// CMP
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case X86::CMP16ri8: return X86::CMP16ri;
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case X86::CMP16mi8: return X86::CMP16mi;
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case X86::CMP32ri8: return X86::CMP32ri;
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case X86::CMP32mi8: return X86::CMP32mi;
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case X86::CMP64ri8: return X86::CMP64ri32;
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case X86::CMP64mi8: return X86::CMP64mi32;
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}
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}
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static unsigned getRelaxedOpcode(unsigned Op) {
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unsigned R = getRelaxedOpcodeArith(Op);
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if (R != Op)
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return R;
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return getRelaxedOpcodeBranch(Op);
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}
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bool X86AsmBackend::MayNeedRelaxation(const MCInst &Inst) const {
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bool X86AsmBackend::MayNeedRelaxation(const MCInst &Inst) const {
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// Branches can always be relaxed.
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if (getRelaxedOpcodeBranch(Inst.getOpcode()) != Inst.getOpcode())
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return true;
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// Check if this instruction is ever relaxable.
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// Check if this instruction is ever relaxable.
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if (getRelaxedOpcode(Inst.getOpcode()) == Inst.getOpcode())
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if (getRelaxedOpcodeArith(Inst.getOpcode()) == Inst.getOpcode())
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return false;
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return false;
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// If so, just assume it can be relaxed. Once we support relaxing more complex
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// instructions we should check that the instruction actually has symbolic
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// Check if it has an expression and is not RIP relative.
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// operands before doing this, but we need to be careful about things like
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bool hasExp = false;
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// PCrel.
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bool hasRIP = false;
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return true;
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for (unsigned i = 0; i < Inst.getNumOperands(); ++i) {
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const MCOperand &Op = Inst.getOperand(i);
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if (Op.isExpr())
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hasExp = true;
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if (Op.isReg() && Op.getReg() == X86::RIP)
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hasRIP = true;
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}
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// FIXME: Why exactly do we need the !hasRIP? Is it just a limitation on
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// how we do relaxations?
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return hasExp && !hasRIP;
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}
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}
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// FIXME: Can tblgen help at all here to verify there aren't other instructions
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// FIXME: Can tblgen help at all here to verify there aren't other instructions
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75
test/MC/ELF/relax-arith.s
Normal file
75
test/MC/ELF/relax-arith.s
Normal file
@ -0,0 +1,75 @@
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// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck %s
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// Test that we correctly relax these instructions into versions that use
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// 16 or 32 bit immediate values.
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bar:
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// CHECK: 'imul'
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// CHECK: ('_section_data', '6669db00 0066691c 25000000 00000069 db000000 00691c25 00000000 00000000 4869db00 00000048 691c2500 00000000 000000')
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.section imul
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imul $foo, %bx, %bx
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imul $foo, bar, %bx
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imul $foo, %ebx, %ebx
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imul $foo, bar, %ebx
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imul $foo, %rbx, %rbx
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imul $foo, bar, %rbx
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// CHECK: and'
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// CHECK:('_section_data', '6681e300 00668124 25000000 00000081 e3000000 00812425 00000000 00000000 4881e300 00000048 81242500 00000000 000000')
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.section and
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and $foo, %bx
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andw $foo, bar
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and $foo, %ebx
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andl $foo, bar
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and $foo, %rbx
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andq $foo, bar
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// CHECK: 'or'
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// CHECK: ('_section_data', '6681cb00 0066810c 25000000 00000081 cb000000 00810c25 00000000 00000000 4881cb00 00000048 810c2500 00000000 000000')
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.section or
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or $foo, %bx
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orw $foo, bar
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or $foo, %ebx
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orl $foo, bar
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or $foo, %rbx
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orq $foo, bar
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// CHECK: 'xor'
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// CHECK: ('_section_data', '6681f300 00668134 25000000 00000081 f3000000 00813425 00000000 00000000 4881f300 00000048 81342500 00000000 000000')
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.section xor
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xor $foo, %bx
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xorw $foo, bar
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xor $foo, %ebx
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xorl $foo, bar
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xor $foo, %rbx
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xorq $foo, bar
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// CHECK: 'add'
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// CHECK: ('_section_data', '6681c300 00668104 25000000 00000081 c3000000 00810425 00000000 00000000 4881c300 00000048 81042500 00000000 000000')
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.section add
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add $foo, %bx
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addw $foo, bar
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add $foo, %ebx
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addl $foo, bar
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add $foo, %rbx
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addq $foo, bar
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// CHECK: 'sub'
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// CHECK: ('_section_data', '6681eb00 0066812c 25000000 00000081 eb000000 00812c25 00000000 00000000 4881eb00 00000048 812c2500 00000000 000000')
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.section sub
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sub $foo, %bx
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subw $foo, bar
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sub $foo, %ebx
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subl $foo, bar
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sub $foo, %rbx
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subq $foo, bar
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// CHECK: 'cmp'
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// CHECK: ('_section_data', '6681fb00 0066813c 25000000 00000081 fb000000 00813c25 00000000 00000000 4881fb00 00000048 813c2500 00000000 000000')
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.section cmp
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cmp $foo, %bx
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cmpw $foo, bar
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cmp $foo, %ebx
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cmpl $foo, bar
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cmp $foo, %rbx
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cmpq $foo, bar
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