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[ARM][LowOverheadLoops] Convert intermediate vpr use assertion to condition
This converts the intermediate VPR use assertion to a condition in the if-statement to protect against assertion failures in case behaviuour is changed. This is a follow-up to https://reviews.llvm.org/D90935 and implements the post-approval comments. Reviewed By: dmgreen Differential Revision: https://reviews.llvm.org/D91790
This commit is contained in:
Sam Tebbs
parent
c0b5fdf2f0
commit
e397da3290
@ -1575,16 +1575,14 @@ void ARMLowOverheadLoops::ConvertVPTBlocks(LowOverheadLoop &LoLoop) {
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!LoLoop.ToRemove.contains(VprDef)) {
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MachineInstr *VCMP = VprDef;
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// The VCMP and VPST can only be merged if the VCMP's operands will have
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// the same values at the VPST
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if (RDA->hasSameReachingDef(VCMP, VPST, VCMP->getOperand(1).getReg()) &&
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// the same values at the VPST.
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// If any of the instructions between the VCMP and VPST are predicated
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// then a different code path is expected to have merged the VCMP and
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// VPST already.
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if (!std::any_of(++MachineBasicBlock::iterator(VCMP),
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MachineBasicBlock::iterator(VPST), hasVPRUse) &&
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RDA->hasSameReachingDef(VCMP, VPST, VCMP->getOperand(1).getReg()) &&
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RDA->hasSameReachingDef(VCMP, VPST, VCMP->getOperand(2).getReg())) {
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// If the instruction after the VCMP is predicated then a different
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// code path is expected to have merged the VCMP and VPST already.
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// This assertion protects against changes to that behaviour
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assert(!std::any_of(++MachineBasicBlock::iterator(VCMP),
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MachineBasicBlock::iterator(VPST), hasVPRUse) &&
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"Instructions between the VCMP and VPST are not expected to "
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"be predicated");
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ReplaceVCMPWithVPT(VCMP, VPST);
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LLVM_DEBUG(dbgs() << "ARM Loops: Removing VPST: " << *VPST);
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LoLoop.ToRemove.insert(VPST);
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@ -17,6 +17,11 @@
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ret void
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}
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define void @combine_kill_flags() {
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while.end6:
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ret void
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}
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define void @no_combination_diff_reg_value() {
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while.end6:
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ret void
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@ -162,7 +167,7 @@ body: |
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; CHECK: renamable $q2 = MVE_VORR renamable $q1, renamable $q1, 0, $noreg, killed renamable $q2
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; CHECK: MVE_VPTv4f32 8, renamable $q1, renamable $q0, 12, implicit-def $vpr
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; CHECK: renamable $q2 = MVE_VORR renamable $q1, renamable $q1, 1, renamable $vpr, killed renamable $q2
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; CHECK: MVE_VPST 4, implicit $vpr
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; CHECK: MVE_VPST 8, implicit $vpr
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; CHECK: dead renamable $q1 = MVE_VORR killed renamable $q1, renamable $q0, 1, killed renamable $vpr, killed renamable $q1
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; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1
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; CHECK: bb.2:
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@ -194,7 +199,7 @@ body: |
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renamable $vpr = MVE_VCMPf32 renamable $q1, renamable $q0, 12, 1, killed renamable $vpr
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MVE_VPST 8, implicit $vpr
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renamable $q2 = MVE_VORR renamable $q1, renamable $q1, 1, renamable $vpr, killed renamable $q2
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MVE_VPST 4, implicit $vpr
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MVE_VPST 8, implicit $vpr
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renamable $q1 = MVE_VORR killed renamable $q1, renamable $q0, 1, renamable $vpr, renamable $q1
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t2LoopEnd renamable $lr, %bb.6, implicit-def dead $cpsr
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tB %bb.8, 14 /* CC::al */, $noreg
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@ -296,6 +301,93 @@ body: |
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bb.9 (align 4):
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CONSTPOOL_ENTRY 0, %const.0, 4
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...
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---
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name: combine_kill_flags
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alignment: 8
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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registers: []
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liveins:
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- { reg: '$r0', virtual-reg: '' }
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- { reg: '$r1', virtual-reg: '' }
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- { reg: '$r2', virtual-reg: '' }
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frameInfo:
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fixedStack: []
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stack:
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- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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callSites: []
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debugValueSubstitutions: []
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constants:
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- id: 0
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value: float 0xC7EFFFFFE0000000
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alignment: 4
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isTargetSpecific: false
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machineFunctionInfo: {}
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body: |
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; CHECK-LABEL: name: combine_kill_flags
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; CHECK: bb.0:
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; CHECK: successors: %bb.1(0x80000000)
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; CHECK: liveins: $q2, $r0, $r1
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; CHECK: renamable $q0 = MVE_VDUP32 renamable $r1, 0, $noreg, undef renamable $q0
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; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1
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; CHECK: bb.1 (align 4):
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; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
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; CHECK: liveins: $lr, $q0, $q2, $r0
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; CHECK: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg
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; CHECK: renamable $q2 = MVE_VORR killed renamable $q2, renamable $q1, 0, $noreg, killed renamable $q2
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; CHECK: MVE_VPTv4f32 8, renamable $q0, killed renamable $q1, 12, implicit-def $vpr
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; CHECK: renamable $q0 = MVE_VORR killed renamable $q0, killed renamable $q0, 1, killed renamable $vpr, killed renamable $q0
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; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1
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; CHECK: bb.2:
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; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
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; CHECK: bb.3 (align 4):
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; CHECK: CONSTPOOL_ENTRY 0, %const.0, 4
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bb.0:
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successors: %bb.6(0x80000000)
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liveins: $r0, $r1, $r2
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renamable $r3, dead $cpsr = nuw nsw tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg
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renamable $q0 = MVE_VDUP32 killed renamable $r1, 0, $noreg, undef renamable $q0
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renamable $r3 = t2ANDri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
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renamable $lr = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
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renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
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renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg
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$lr = t2DoLoopStart renamable $lr
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bb.6 (align 4):
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successors: %bb.6(0x7c000000), %bb.8(0x04000000)
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liveins: $lr, $q0, $r0, $r1, $r2, $q2
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renamable $lr = t2LoopDec killed renamable $lr, 1
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renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg
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renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
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MVE_VPST 2, implicit $vpr
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renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr
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renamable $vpr = MVE_VCMPf32 renamable $q0, renamable $q1, 12, 1, killed renamable $vpr
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renamable $q2 = MVE_VORR renamable $q2, killed renamable $q1, 0, $noreg, killed renamable $q2
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MVE_VPST 8, implicit $vpr
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renamable $q0 = MVE_VORR renamable $q0, renamable $q0, 1, renamable $vpr, killed renamable $q0
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t2LoopEnd renamable $lr, %bb.6, implicit-def dead $cpsr
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tB %bb.8, 14 /* CC::al */, $noreg
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bb.8:
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liveins: $r2, $r12, $q0
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frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
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bb.9 (align 4):
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CONSTPOOL_ENTRY 0, %const.0, 4
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...
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---
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name: no_combination_diff_reg_value
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