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[AArch64][SVE] Added GPR64shifted and GPR64NoXZRshifted register classes.
Summary: This is patch [3/4] in a series to add assembler/disassembler support for SVE's contiguous LD1 (scalar+scalar) instructions: - Patch [1/4]: https://reviews.llvm.org/D45687 - Patch [2/4]: https://reviews.llvm.org/D45688 - Patch [3/4]: https://reviews.llvm.org/D45689 - Patch [4/4]: https://reviews.llvm.org/D45690 Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro Reviewed By: SjoerdMeijer Subscribers: tschuett, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D45689 llvm-svn: 330406
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@ -933,3 +933,24 @@ def ZZZZ_s : RegisterOperand<ZPR4, "printTypedVectorList<0,'s'>"> {
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def ZZZZ_d : RegisterOperand<ZPR4, "printTypedVectorList<0,'d'>"> {
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def ZZZZ_d : RegisterOperand<ZPR4, "printTypedVectorList<0,'d'>"> {
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let ParserMatchClass = ZPRVectorList<64, 4>;
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let ParserMatchClass = ZPRVectorList<64, 4>;
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}
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}
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class GPR64ShiftExtendAsmOperand <string AsmOperandName, int Scale, string RegClass> : AsmOperandClass {
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let Name = AsmOperandName # Scale;
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let PredicateMethod = "isGPR64WithShiftExtend<AArch64::"#RegClass#"RegClassID, " # Scale # ">";
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let DiagnosticType = "Invalid" # AsmOperandName # Scale;
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let RenderMethod = "addRegOperands";
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let ParserMethod = "tryParseGPROperand<true>";
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}
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class GPR64ExtendRegisterOperand<string Name, int Scale, RegisterClass RegClass> : RegisterOperand<RegClass>{
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let ParserMatchClass = !cast<AsmOperandClass>(Name);
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let PrintMethod = "printRegWithShiftExtend<false, " # Scale # ", 'x'>";
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}
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foreach Scale = [8, 16, 32, 64] in {
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def GPR64shiftedAsmOpnd # Scale : GPR64ShiftExtendAsmOperand<"GPR64shifted", Scale, "GPR64">;
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def GPR64shifted # Scale : GPR64ExtendRegisterOperand<"GPR64shiftedAsmOpnd" # Scale, Scale, GPR64>;
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def GPR64NoXZRshiftedAsmOpnd # Scale : GPR64ShiftExtendAsmOperand<"GPR64NoXZRshifted", Scale, "GPR64common">;
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def GPR64NoXZRshifted # Scale : GPR64ExtendRegisterOperand<"GPR64NoXZRshiftedAsmOpnd" # Scale, Scale, GPR64common>;
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}
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@ -3823,6 +3823,22 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
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ComputeAvailableFeatures(STI->getFeatureBits()));
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ComputeAvailableFeatures(STI->getFeatureBits()));
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return Error(Loc, "unrecognized instruction mnemonic" + Suggestion);
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return Error(Loc, "unrecognized instruction mnemonic" + Suggestion);
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}
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}
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case Match_InvalidGPR64shifted8:
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return Error(Loc, "register must be x0..x30 or xzr, without shift");
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case Match_InvalidGPR64shifted16:
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return Error(Loc, "register must be x0..x30 or xzr, with required shift 'lsl #1'");
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case Match_InvalidGPR64shifted32:
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return Error(Loc, "register must be x0..x30 or xzr, with required shift 'lsl #2'");
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case Match_InvalidGPR64shifted64:
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return Error(Loc, "register must be x0..x30 or xzr, with required shift 'lsl #3'");
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case Match_InvalidGPR64NoXZRshifted8:
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return Error(Loc, "register must be x0..x30 without shift");
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case Match_InvalidGPR64NoXZRshifted16:
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return Error(Loc, "register must be x0..x30 with required shift 'lsl #1'");
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case Match_InvalidGPR64NoXZRshifted32:
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return Error(Loc, "register must be x0..x30 with required shift 'lsl #2'");
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case Match_InvalidGPR64NoXZRshifted64:
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return Error(Loc, "register must be x0..x30 with required shift 'lsl #3'");
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case Match_InvalidSVEPattern:
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case Match_InvalidSVEPattern:
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return Error(Loc, "invalid predicate pattern");
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return Error(Loc, "invalid predicate pattern");
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case Match_InvalidSVEPredicateAnyReg:
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case Match_InvalidSVEPredicateAnyReg:
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@ -4268,6 +4284,14 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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case Match_InvalidLabel:
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case Match_InvalidLabel:
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case Match_InvalidComplexRotationEven:
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case Match_InvalidComplexRotationEven:
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case Match_InvalidComplexRotationOdd:
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case Match_InvalidComplexRotationOdd:
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case Match_InvalidGPR64shifted8:
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case Match_InvalidGPR64shifted16:
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case Match_InvalidGPR64shifted32:
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case Match_InvalidGPR64shifted64:
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case Match_InvalidGPR64NoXZRshifted8:
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case Match_InvalidGPR64NoXZRshifted16:
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case Match_InvalidGPR64NoXZRshifted32:
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case Match_InvalidGPR64NoXZRshifted64:
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case Match_InvalidSVEPredicateAnyReg:
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case Match_InvalidSVEPredicateAnyReg:
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case Match_InvalidSVEPattern:
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case Match_InvalidSVEPattern:
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case Match_InvalidSVEPredicateBReg:
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case Match_InvalidSVEPredicateBReg:
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@ -55,6 +55,10 @@ static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
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static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
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static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t Address,
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uint64_t Address,
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const void *Decoder);
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const void *Decoder);
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LLVM_ATTRIBUTE_UNUSED
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static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
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static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t Address,
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uint64_t Address,
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const void *Decoder);
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const void *Decoder);
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@ -402,6 +406,17 @@ static const unsigned GPR64DecoderTable[] = {
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AArch64::LR, AArch64::XZR
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AArch64::LR, AArch64::XZR
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};
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};
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static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t Addr,
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const void *Decoder) {
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if (RegNo > 30)
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return Fail;
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unsigned Register = GPR64DecoderTable[RegNo];
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Inst.addOperand(MCOperand::createReg(Register));
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return Success;
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}
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static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
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static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t Addr,
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uint64_t Addr,
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const void *Decoder) {
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const void *Decoder) {
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@ -969,12 +969,9 @@ void AArch64InstPrinter::printArithExtend(const MCInst *MI, unsigned OpNum,
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O << " #" << ShiftVal;
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O << " #" << ShiftVal;
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}
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}
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void AArch64InstPrinter::printMemExtend(const MCInst *MI, unsigned OpNum,
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static void printMemExtendImpl(bool SignExtend, bool DoShift,
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raw_ostream &O, char SrcRegKind,
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unsigned Width, char SrcRegKind,
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unsigned Width) {
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raw_ostream &O) {
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unsigned SignExtend = MI->getOperand(OpNum).getImm();
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unsigned DoShift = MI->getOperand(OpNum + 1).getImm();
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// sxtw, sxtx, uxtw or lsl (== uxtx)
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// sxtw, sxtx, uxtw or lsl (== uxtx)
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bool IsLSL = !SignExtend && SrcRegKind == 'x';
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bool IsLSL = !SignExtend && SrcRegKind == 'x';
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if (IsLSL)
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if (IsLSL)
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@ -986,6 +983,28 @@ void AArch64InstPrinter::printMemExtend(const MCInst *MI, unsigned OpNum,
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O << " #" << Log2_32(Width / 8);
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O << " #" << Log2_32(Width / 8);
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}
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}
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void AArch64InstPrinter::printMemExtend(const MCInst *MI, unsigned OpNum,
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raw_ostream &O, char SrcRegKind,
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unsigned Width) {
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bool SignExtend = MI->getOperand(OpNum).getImm();
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bool DoShift = MI->getOperand(OpNum + 1).getImm();
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printMemExtendImpl(SignExtend, DoShift, Width, SrcRegKind, O);
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}
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template <bool SignExtend, int ExtWidth, char SrcRegKind>
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void AArch64InstPrinter::printRegWithShiftExtend(const MCInst *MI,
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unsigned OpNum,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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printOperand(MI, OpNum, STI, O);
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bool DoShift = ExtWidth != 8;
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if (SignExtend || DoShift || SrcRegKind == 'w') {
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O << ", ";
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printMemExtendImpl(SignExtend, DoShift, ExtWidth, SrcRegKind, O);
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}
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}
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void AArch64InstPrinter::printCondCode(const MCInst *MI, unsigned OpNum,
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void AArch64InstPrinter::printCondCode(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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raw_ostream &O) {
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@ -90,7 +90,9 @@ protected:
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const MCSubtargetInfo &STI, raw_ostream &O) {
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const MCSubtargetInfo &STI, raw_ostream &O) {
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printMemExtend(MI, OpNum, O, SrcRegKind, Width);
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printMemExtend(MI, OpNum, O, SrcRegKind, Width);
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}
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}
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template <bool SignedExtend, int ExtWidth, char SrcRegKind>
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void printRegWithShiftExtend(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI, raw_ostream &O);
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void printCondCode(const MCInst *MI, unsigned OpNum,
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void printCondCode(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI, raw_ostream &O);
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const MCSubtargetInfo &STI, raw_ostream &O);
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void printInverseCondCode(const MCInst *MI, unsigned OpNum,
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void printInverseCondCode(const MCInst *MI, unsigned OpNum,
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