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[PowerPC] Make no-PIC default to match GCC - LLVM

Browse Source 
Set -fno-PIC as the default option.

Differential Revision: https://reviews.llvm.org/D53383

llvm-svn: 347069
This commit is contained in:
Stefan Pintilie 2018-11-16 18:36:21 +00:00
parent a6180e2036
commit e3d9879744
81 changed files with 516 additions and 585 deletions
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6
lib/Target/PowerPC/PPCTargetMachine.cpp
View File

@ -214,11 +214,7 @@ static Reloc::Model getEffectiveRelocModel(const Triple &TT,
if (TT.isOSDarwin())
return Reloc::DynamicNoPIC;
// Non-darwin 64-bit platforms are PIC by default.
if (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le)
return Reloc::PIC_;
// 32-bit is static by default.
// Otherwise is static by default.
return Reloc::Static;
}

2
test/CodeGen/PowerPC/MCSE-caller-preserved-reg.ll
View File

@ -1,4 +1,4 @@
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
; The instructions addis,addi, bl are used to calculate the address of TLS
; thread local variables. These TLS access code sequences are generated
; repeatedly every time the thread local variable is accessed. By communicating

1
test/CodeGen/PowerPC/addegluecrash.ll
View File

@ -27,6 +27,7 @@ define void @bn_mul_comba8(i64* nocapture %r, i64* nocapture readonly %a, i64* n
; CHECK-NEXT: mr 4, 10
; CHECK-NEXT: clrldi 4, 4, 32
; CHECK-NEXT: std 4, 0(3)
; CHECK-NEXT: std 6, -8(1) # 8-byte Folded Spill
; CHECK-NEXT: blr
%1 = load i64, i64* %a, align 8
%conv = zext i64 %1 to i128

6
test/CodeGen/PowerPC/atomics-constant.ll
View File

@ -8,14 +8,14 @@ target triple = "powerpc64le-unknown-linux-gnu"
define i64 @foo() {
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis 3, 2, .LC0@toc@ha
; CHECK-NEXT: addis 3, 2, a@toc@ha
; CHECK-NEXT: li 4, 0
; CHECK-NEXT: ld 3, .LC0@toc@l(3)
; CHECK-NEXT: addi 3, 3, a@toc@l
; CHECK-NEXT: cmpd 7, 4, 4
; CHECK-NEXT: ld 3, 0(3)
; CHECK-NEXT: li 3, 0
; CHECK-NEXT: bne- 7, .+4
; CHECK-NEXT: isync
; CHECK-NEXT: li 3, 0
; CHECK-NEXT: blr
entry:
%value = load atomic i64, i64* @a acquire, align 8

4
test/CodeGen/PowerPC/f128-aggregates.ll
View File

@ -1,7 +1,7 @@
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
; RUN: -enable-ppc-quad-precision -verify-machineinstrs \
; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-unknown \
; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64-unknown-unknown \
; RUN: -enable-ppc-quad-precision -verify-machineinstrs \
; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s \
; RUN: | FileCheck -check-prefix=CHECK-BE %s

2
test/CodeGen/PowerPC/f128-conv.ll
View File

@ -1,4 +1,4 @@
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
; RUN: -enable-ppc-quad-precision -ppc-vsr-nums-as-vr \
; RUN: -verify-machineinstrs -ppc-asm-full-reg-names < %s | FileCheck %s

2
test/CodeGen/PowerPC/f128-truncateNconv.ll
View File

@ -1,4 +1,4 @@
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
; RUN: -verify-machineinstrs -enable-ppc-quad-precision \
; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s

2
test/CodeGen/PowerPC/f128-vecExtractNconv.ll
View File

@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown -ppc-vsr-nums-as-vr \
; RUN: -ppc-asm-full-reg-names -verify-machineinstrs \
; RUN: -relocation-model=pic -ppc-asm-full-reg-names -verify-machineinstrs \
; RUN: -enable-ppc-quad-precision < %s | FileCheck %s
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-unknown -ppc-vsr-nums-as-vr \
; RUN: -ppc-asm-full-reg-names -verify-machineinstrs \

2
test/CodeGen/PowerPC/fast-isel-call.ll
View File

@ -2,7 +2,7 @@
; registers and with -fast-isel-abort=1 turned on the test case will then fail.
; When fastisel better supports VSX fix up this test case.
;
; RUN: llc < %s -O0 -verify-machineinstrs -mattr=-vsx -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -ppc-late-peephole=true | FileCheck %s --check-prefix=ELF64
; RUN: llc < %s -O0 -relocation-model=pic -verify-machineinstrs -mattr=-vsx -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -ppc-late-peephole=true | FileCheck %s --check-prefix=ELF64
define i32 @t1(i8 signext %a) nounwind {
%1 = sext i8 %a to i32

4
test/CodeGen/PowerPC/func-addr-consts.ll
View File

@ -12,5 +12,5 @@ entry:
ret void
}
; CHECK: .section gsection,"aw",@progbits
; CHECK: .section hsection,"aw",@progbits
; CHECK: .section gsection,"a",@progbits
; CHECK: .section hsection,"a",@progbits

4
test/CodeGen/PowerPC/mcm-13.ll
View File

@ -1,5 +1,5 @@
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=medium <%s | FileCheck %s
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=large <%s | FileCheck %s
; RUN: llc -relocation-model=pic -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=medium <%s | FileCheck %s
; RUN: llc -relocation-model=pic -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=large <%s | FileCheck %s
; Test correct code generation for medium and large code model
; for loading and storing a weak variable

4
test/CodeGen/PowerPC/mcm-6.ll
View File

@ -1,5 +1,5 @@
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=medium < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=large < %s | FileCheck %s
; RUN: llc -relocation-model=pic -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=medium < %s | FileCheck %s
; RUN: llc -relocation-model=pic -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=large < %s | FileCheck %s
; Test correct code generation for medium and large code model
; for loading and storing a tentatively defined variable.

4
test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll
View File

@ -1,8 +1,8 @@
; RUN: llc < %s -ppc-vsr-nums-as-vr -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -verify-machineinstrs -ppc-asm-full-reg-names -mcpu=pwr8 \
; RUN: -verify-machineinstrs -ppc-asm-full-reg-names -mcpu=pwr8 -relocation-model=pic \
; RUN: | FileCheck %s
; RUN: llc < %s -ppc-vsr-nums-as-vr -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -verify-machineinstrs -ppc-asm-full-reg-names -mcpu=pwr8 \
; RUN: -verify-machineinstrs -ppc-asm-full-reg-names -mcpu=pwr8 -relocation-model=pic \
; RUN: | FileCheck %s -check-prefix=CHECK-LE
; The build[csilf] functions simply test the scalar_to_vector handling with

12
test/CodeGen/PowerPC/ppc64-blnop.ll
View File

@ -1,11 +1,11 @@
; RUN: llc < %s -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s
; RUN: llc < %s -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s
; RUN: llc < %s -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s
; RUN: llc < %s -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s
; RUN: llc < %s -function-sections -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s -check-prefix=CHECK-FS
; RUN: llc < %s -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s
; RUN: llc < %s -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s
; RUN: llc < %s -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s
; RUN: llc < %s -relocation-model=pic -function-sections -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s -check-prefix=CHECK-FS
; RUN: llc < %s -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s
; RUN: llc < %s -function-sections -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s -check-prefix=CHECK-FS
; RUN: llc < %s -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: llc < %s -relocation-model=pic -function-sections -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s -check-prefix=CHECK-FS
; RUN: llc < %s -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -code-model=small -mcpu=pwr8 | FileCheck %s -check-prefix=SCM
%class.T = type { [2 x i8] }

18
test/CodeGen/PowerPC/ppc64-i128-abi.ll
View File

@ -1,33 +1,33 @@
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr8 < %s | FileCheck %s -check-prefix=CHECK-LE \
; RUN: --implicit-check-not xxswapd
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr8 < %s | FileCheck %s -check-prefix=CHECK-BE
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-NOVSX
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-NOVSX \
; RUN: --implicit-check-not xxswapd
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-BE-NOVSX
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr8 -mattr=-vsx < %s | \
; RUN: FileCheck %s -check-prefix=CHECK-LE-NOVSX --implicit-check-not xxswapd
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s -check-prefix=CHECK-P9 --implicit-check-not xxswapd
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr9 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-NOVSX \
; RUN: --implicit-check-not xxswapd
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr9 -mattr=-power9-vector -mattr=-direct-move < %s | \
; RUN: FileCheck %s -check-prefix=CHECK-LE --implicit-check-not xxswapd

6
test/CodeGen/PowerPC/ppc64le-aggregates.ll
View File

@ -1,8 +1,8 @@
; RUN: llc -verify-machineinstrs < %s -mcpu=pwr8 \
; RUN: llc -relocation-model=pic -verify-machineinstrs < %s -mcpu=pwr8 \
; RUN: -mattr=+altivec -mattr=-vsx | FileCheck %s
; RUN: llc -verify-machineinstrs < %s -mattr=+altivec \
; RUN: llc -relocation-model=pic -verify-machineinstrs < %s -mattr=+altivec \
; RUN: -mattr=-vsx | FileCheck %s
; RUN: llc -verify-machineinstrs < %s -mcpu=pwr9 \
; RUN: llc -relocation-model=pic -verify-machineinstrs < %s -mcpu=pwr9 \
; RUN: -mattr=-direct-move -mattr=+altivec | FileCheck %s
; Currently VSX support is disabled for this test because we generate lxsdx

2
test/CodeGen/PowerPC/ppcf128-endian.ll
View File

@ -1,4 +1,4 @@
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec -mattr=-vsx < %s | FileCheck %s
; RUN: llc -relocation-model=pic -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec -mattr=-vsx < %s | FileCheck %s
target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu"

15
test/CodeGen/PowerPC/pr32140.ll
View File

@ -10,7 +10,10 @@
define void @bswapStorei64Toi32() {
; CHECK-LABEL: bswapStorei64Toi32:
; CHECK: # %bb.0: # %entry
; CHECK: lwa 3, 0(3)
; CHECK-NEXT: addis 3, 2, ai@toc@ha
; CHECK-NEXT: addis 4, 2, bi@toc@ha
; CHECK-NEXT: lwa 3, ai@toc@l(3)
; CHECK-NEXT: addi 4, 4, bi@toc@l
; CHECK-NEXT: rldicl 3, 3, 32, 32
; CHECK-NEXT: stwbrx 3, 0, 4
; CHECK-NEXT: blr
@ -26,7 +29,10 @@ entry:
define void @bswapStorei32Toi16() {
; CHECK-LABEL: bswapStorei32Toi16:
; CHECK: # %bb.0: # %entry
; CHECK: lha 3, 0(3)
; CHECK-NEXT: addis 3, 2, as@toc@ha
; CHECK-NEXT: addis 4, 2, bs@toc@ha
; CHECK-NEXT: lha 3, as@toc@l(3)
; CHECK-NEXT: addi 4, 4, bs@toc@l
; CHECK-NEXT: srwi 3, 3, 16
; CHECK-NEXT: sthbrx 3, 0, 4
; CHECK-NEXT: blr
@ -42,7 +48,10 @@ entry:
define void @bswapStorei64Toi16() {
; CHECK-LABEL: bswapStorei64Toi16:
; CHECK: # %bb.0: # %entry
; CHECK: lha 3, 0(3)
; CHECK-NEXT: addis 3, 2, as@toc@ha
; CHECK-NEXT: addis 4, 2, bs@toc@ha
; CHECK-NEXT: lha 3, as@toc@l(3)
; CHECK-NEXT: addi 4, 4, bs@toc@l
; CHECK-NEXT: rldicl 3, 3, 16, 48
; CHECK-NEXT: sthbrx 3, 0, 4
; CHECK-NEXT: blr

3
test/CodeGen/PowerPC/preemption.ll
View File

@ -1,4 +1,5 @@
; RUN: llc -mtriple powerpc64le-unkown-gnu-linux < %s | FileCheck %s
; RUN: llc -mtriple powerpc64le-unkown-gnu-linux -relocation-model=pic \
; RUN: < %s | FileCheck %s
; RUN: llc -mtriple powerpc64le-unkown-gnu-linux -relocation-model=static \
; RUN: < %s | FileCheck --check-prefix=STATIC %s
; RUN: llc -mtriple powerpc64le-unkown-gnu-linux -relocation-model=pic \

4
test/CodeGen/PowerPC/save-bp.ll
View File

@ -1,6 +1,6 @@
; RUN: llc -mtriple=ppc64-- -ppc-always-use-base-pointer < %s | FileCheck %s --check-prefix CHECK --check-prefix PPC64
; RUN: llc -ppc-always-use-base-pointer < %s | FileCheck %s --check-prefix CHECK --check-prefix PPC32
; RUN: llc -ppc-always-use-base-pointer -relocation-model pic < %s | FileCheck %s --check-prefix CHECK --check-prefix PPC32PIC
; RUN: llc -ppc-always-use-base-pointer -relocation-model=static < %s | FileCheck %s --check-prefix CHECK --check-prefix PPC32
; RUN: llc -ppc-always-use-base-pointer -relocation-model=pic < %s | FileCheck %s --check-prefix CHECK --check-prefix PPC32PIC
; CHECK-LABEL: fred:

6
test/CodeGen/PowerPC/sjlj_no0x.ll
View File

@ -1,6 +1,6 @@
; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -relocation-model=pic -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -relocation-model=pic -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -relocation-model=pic -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -verify-machineinstrs | FileCheck %s
target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu"

6
test/CodeGen/PowerPC/swaps-le-6.ll
View File

@ -1,13 +1,13 @@
; RUN: llc -verify-machineinstrs -mcpu=pwr8 -ppc-vsr-nums-as-vr \
; RUN: llc -relocation-model=pic -verify-machineinstrs -mcpu=pwr8 -ppc-vsr-nums-as-vr \
; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -O3 < %s | FileCheck %s
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -O3 \
; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -O3 \
; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs \
; RUN: < %s | FileCheck %s --check-prefix=CHECK-P9 \
; RUN: --implicit-check-not xxswapd
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -O3 \
; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -O3 \
; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs \
; RUN: -mattr=-power9-vector < %s | FileCheck %s

4
test/CodeGen/PowerPC/testComparesi32gtu.ll
View File

@ -1,7 +1,7 @@
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl

4
test/CodeGen/PowerPC/testComparesi32ltu.ll
View File

@ -1,7 +1,7 @@
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl

20
test/CodeGen/PowerPC/testComparesieqsc.ll
View File

@ -69,12 +69,11 @@ entry:
define void @test_ieqsc_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_ieqsc_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, %b
@ -87,13 +86,12 @@ entry:
define void @test_ieqsc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_ieqsc_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, %b
@ -106,11 +104,10 @@ entry:
define void @test_ieqsc_z_store(i8 signext %a) {
; CHECK-LABEL: test_ieqsc_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: stb r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, 0
@ -123,12 +120,11 @@ entry:
define void @test_ieqsc_sext_z_store(i8 signext %a) {
; CHECK-LABEL: test_ieqsc_sext_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: stb r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, 0

20
test/CodeGen/PowerPC/testComparesieqsi.ll
View File

@ -69,12 +69,11 @@ entry:
define void @test_ieqsi_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_ieqsi_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, %b
@ -87,13 +86,12 @@ entry:
define void @test_ieqsi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_ieqsi_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, %b
@ -106,11 +104,10 @@ entry:
define void @test_ieqsi_z_store(i32 signext %a) {
; CHECK-LABEL: test_ieqsi_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: stw r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, 0
@ -123,12 +120,11 @@ entry:
define void @test_ieqsi_sext_z_store(i32 signext %a) {
; CHECK-LABEL: test_ieqsi_sext_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: stw r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, 0

20
test/CodeGen/PowerPC/testComparesieqsll.ll
View File

@ -67,12 +67,11 @@ entry:
define void @test_ieqsll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_ieqsll_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
@ -85,12 +84,11 @@ entry:
define void @test_ieqsll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_ieqsll_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
@ -103,11 +101,10 @@ entry:
define void @test_ieqsll_z_store(i64 %a) {
; CHECK-LABEL: test_ieqsll_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, 0
@ -120,11 +117,10 @@ entry:
define void @test_ieqsll_sext_z_store(i64 %a) {
; CHECK-LABEL: test_ieqsll_sext_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, 0

20
test/CodeGen/PowerPC/testComparesieqss.ll
View File

@ -69,12 +69,11 @@ entry:
define void @test_ieqss_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_ieqss_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, %b
@ -87,13 +86,12 @@ entry:
define void @test_ieqss_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_ieqss_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, %b
@ -106,11 +104,10 @@ entry:
define void @test_ieqss_z_store(i16 signext %a) {
; CHECK-LABEL: test_ieqss_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: sth r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, 0
@ -123,12 +120,11 @@ entry:
define void @test_ieqss_sext_z_store(i16 signext %a) {
; CHECK-LABEL: test_ieqss_sext_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: sth r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, 0

20
test/CodeGen/PowerPC/testComparesiequc.ll
View File

@ -69,12 +69,11 @@ entry:
define void @test_iequc_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_iequc_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, %b
@ -87,13 +86,12 @@ entry:
define void @test_iequc_sext_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_iequc_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, %b
@ -106,11 +104,10 @@ entry:
define void @test_iequc_z_store(i8 zeroext %a) {
; CHECK-LABEL: test_iequc_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: stb r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, 0
@ -123,12 +120,11 @@ entry:
define void @test_iequc_sext_z_store(i8 zeroext %a) {
; CHECK-LABEL: test_iequc_sext_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: stb r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, 0

20
test/CodeGen/PowerPC/testComparesiequi.ll
View File

@ -69,12 +69,11 @@ entry:
define void @test_iequi_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_iequi_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, %b
@ -87,13 +86,12 @@ entry:
define void @test_iequi_sext_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_iequi_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, %b
@ -106,11 +104,10 @@ entry:
define void @test_iequi_z_store(i32 zeroext %a) {
; CHECK-LABEL: test_iequi_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: stw r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, 0
@ -123,12 +120,11 @@ entry:
define void @test_iequi_sext_z_store(i32 zeroext %a) {
; CHECK-LABEL: test_iequi_sext_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: stw r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, 0

20
test/CodeGen/PowerPC/testComparesiequll.ll
View File

@ -67,12 +67,11 @@ entry:
define void @test_iequll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_iequll_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
@ -85,12 +84,11 @@ entry:
define void @test_iequll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_iequll_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
@ -103,11 +101,10 @@ entry:
define void @test_iequll_z_store(i64 %a) {
; CHECK-LABEL: test_iequll_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, 0
@ -120,11 +117,10 @@ entry:
define void @test_iequll_sext_z_store(i64 %a) {
; CHECK-LABEL: test_iequll_sext_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, 0

20
test/CodeGen/PowerPC/testComparesiequs.ll
View File

@ -69,12 +69,11 @@ entry:
define void @test_iequs_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_iequs_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, %b
@ -87,13 +86,12 @@ entry:
define void @test_iequs_sext_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_iequs_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, %b
@ -106,11 +104,10 @@ entry:
define void @test_iequs_z_store(i16 zeroext %a) {
; CHECK-LABEL: test_iequs_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: sth r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, 0
@ -123,12 +120,11 @@ entry:
define void @test_iequs_sext_z_store(i16 zeroext %a) {
; CHECK-LABEL: test_iequs_sext_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: sth r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, 0

10
test/CodeGen/PowerPC/testComparesigesc.ll
View File

@ -36,12 +36,11 @@ entry:
define void @test_igesc_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_igesc_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i8 %a, %b
@ -53,12 +52,11 @@ entry:
define void @test_igesc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_igesc_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i8 %a, %b

10
test/CodeGen/PowerPC/testComparesigesi.ll
View File

@ -36,12 +36,11 @@ entry:
define void @test_igesi_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_igesi_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i32 %a, %b
@ -53,12 +52,11 @@ entry:
define void @test_igesi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_igesi_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i32 %a, %b

28
test/CodeGen/PowerPC/testComparesigesll.ll
View File

@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i64 0, align 8
define signext i32 @test_igesll(i64 %a, i64 %b) {
@ -63,11 +63,12 @@ entry:
define void @test_igesll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_igesll_store:
; CHECK: # %bb.0: # %entry
; CHECK: sradi r6, r3, 63
; CHECK: subfc r3, r4, r3
; CHECK: rldicl r3, r4, 1, 63
; CHECK: adde r3, r6, r3
; CHECK: std r3
; CHECK-NEXT: sradi r6, r3, 63
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: subfc r3, r4, r3
; CHECK-NEXT: rldicl r3, r4, 1, 63
; CHECK-NEXT: adde r3, r6, r3
; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i64 %a, %b
@ -80,13 +81,12 @@ define void @test_igesll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_igesll_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r6, r3, 63
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: subfc r3, r4, r3
; CHECK-NEXT: rldicl r3, r4, 1, 63
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: adde r3, r6, r3
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i64 %a, %b
@ -98,11 +98,10 @@ entry:
define void @test_igesll_z_store(i64 %a) {
; CHECK-LABEL: test_igesll_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: not r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i64 %a, -1
@ -114,11 +113,10 @@ entry:
define void @test_igesll_sext_z_store(i64 %a) {
; CHECK-LABEL: test_igesll_sext_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: not r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: std r3,
; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i64 %a, -1

10
test/CodeGen/PowerPC/testComparesigess.ll
View File

@ -36,12 +36,11 @@ entry:
define void @test_igess_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_igess_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i16 %a, %b
@ -53,12 +52,11 @@ entry:
define void @test_igess_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_igess_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i16 %a, %b

4
test/CodeGen/PowerPC/testComparesigtsc.ll
View File

@ -1,7 +1,7 @@
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl

4
test/CodeGen/PowerPC/testComparesigtsi.ll
View File

@ -1,7 +1,7 @@
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl

4
test/CodeGen/PowerPC/testComparesigtsll.ll
View File

@ -1,7 +1,7 @@
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl

4
test/CodeGen/PowerPC/testComparesigtss.ll
View File

@ -1,7 +1,7 @@
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl

4
test/CodeGen/PowerPC/testComparesigtuc.ll
View File

@ -1,7 +1,7 @@
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl

4
test/CodeGen/PowerPC/testComparesigtui.ll
View File

@ -1,7 +1,7 @@
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl

4
test/CodeGen/PowerPC/testComparesigtus.ll
View File

@ -1,7 +1,7 @@
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl

10
test/CodeGen/PowerPC/testComparesilesc.ll
View File

@ -36,12 +36,11 @@ entry:
define void @test_ilesc_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_ilesc_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i8 %a, %b
@ -53,12 +52,11 @@ entry:
define void @test_ilesc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_ilesc_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i8 %a, %b

10
test/CodeGen/PowerPC/testComparesilesi.ll
View File

@ -36,12 +36,11 @@ entry:
define void @test_ilesi_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_ilesi_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i32 %a, %b
@ -53,12 +52,11 @@ entry:
define void @test_ilesi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_ilesi_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i32 %a, %b

20
test/CodeGen/PowerPC/testComparesilesll.ll
View File

@ -65,13 +65,12 @@ entry:
define void @test_ilesll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_ilesll_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sradi r6, r4, 63
; CHECK-NEXT: ld r5, .LC0@toc@l(r5)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: subfc r4, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: adde r3, r6, r3
; CHECK-NEXT: std r3, 0(r5)
; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i64 %a, %b
@ -84,13 +83,12 @@ define void @test_ilesll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_ilesll_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r6, r4, 63
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: subfc r4, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: adde r3, r6, r3
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i64 %a, %b
@ -102,12 +100,11 @@ entry:
define void @test_ilesll_z_store(i64 %a) {
; CHECK-LABEL: test_ilesll_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: addi r5, r3, -1
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: or r3, r5, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i64 %a, 1
@ -119,12 +116,11 @@ entry:
define void @test_ilesll_sext_z_store(i64 %a) {
; CHECK-LABEL: test_ilesll_sext_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: addi r5, r3, -1
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: or r3, r5, r3
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i64 %a, 1

10
test/CodeGen/PowerPC/testComparesiless.ll
View File

@ -36,12 +36,11 @@ entry:
define void @test_iless_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iless_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i16 %a, %b
@ -53,12 +52,11 @@ entry:
define void @test_iless_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iless_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i16 %a, %b

62
test/CodeGen/PowerPC/testComparesinesc.ll
View File

@ -1,16 +1,17 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i8 0, align 1
define signext i32 @test_inesc(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_inesc:
; CHECK: xor r3, r3, r4
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
@ -23,7 +24,8 @@ entry:
define signext i32 @test_inesc_sext(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_inesc_sext:
; CHECK: xor r3, r3, r4
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
@ -37,7 +39,8 @@ entry:
define signext i32 @test_inesc_z(i8 signext %a) {
; CHECK-LABEL: test_inesc_z:
; CHECK: cntlzw r3, r3
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
@ -49,7 +52,8 @@ entry:
define signext i32 @test_inesc_sext_z(i8 signext %a) {
; CHECK-LABEL: test_inesc_sext_z:
; CHECK: cntlzw r3, r3
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
@ -62,11 +66,13 @@ entry:
define void @test_inesc_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_inesc_store:
; CHECK: xor r3, r3, r4
; CHECK: cntlzw r3, r3
; CHECK: srwi r3, r3, 5
; CHECK: xori r3, r3, 1
; CHECK: stb r3, 0(r4)
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, %b
@ -77,12 +83,14 @@ entry:
define void @test_inesc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_inesc_sext_store:
; CHECK: xor r3, r3, r4
; CHECK: cntlzw r3, r3
; CHECK: srwi r3, r3, 5
; CHECK: xori r3, r3, 1
; CHECK: neg r3, r3
; CHECK: stb r3, 0(r4)
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, %b
@ -93,10 +101,12 @@ entry:
define void @test_inesc_z_store(i8 signext %a) {
; CHECK-LABEL: test_inesc_z_store:
; CHECK: cntlzw r3, r3
; CHECK: srwi r3, r3, 5
; CHECK: xori r3, r3, 1
; CHECK: stb r3, 0(r4)
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stb r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, 0
@ -107,11 +117,13 @@ entry:
define void @test_inesc_sext_z_store(i8 signext %a) {
; CHECK-LABEL: test_inesc_sext_z_store:
; CHECK: cntlzw r3, r3
; CHECK: srwi r3, r3, 5
; CHECK: xori r3, r3, 1
; CHECK: neg r3, r3
; CHECK: stb r3, 0(r4)
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stb r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, 0

62
test/CodeGen/PowerPC/testComparesinesi.ll
View File

@ -1,16 +1,17 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i32 0, align 4
define signext i32 @test_inesi(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_inesi:
; CHECK: xor r3, r3, r4
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
@ -23,7 +24,8 @@ entry:
define signext i32 @test_inesi_sext(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_inesi_sext:
; CHECK: xor r3, r3, r4
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
@ -37,7 +39,8 @@ entry:
define signext i32 @test_inesi_z(i32 signext %a) {
; CHECK-LABEL: test_inesi_z:
; CHECK: cntlzw r3, r3
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
@ -49,7 +52,8 @@ entry:
define signext i32 @test_inesi_sext_z(i32 signext %a) {
; CHECK-LABEL: test_inesi_sext_z:
; CHECK: cntlzw r3, r3
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
@ -62,11 +66,13 @@ entry:
define void @test_inesi_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_inesi_store:
; CHECK: xor r3, r3, r4
; CHECK: cntlzw r3, r3
; CHECK: srwi r3, r3, 5
; CHECK: xori r3, r3, 1
; CHECK: stw r3, 0(r4)
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, %b
@ -77,12 +83,14 @@ entry:
define void @test_inesi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_inesi_sext_store:
; CHECK: xor r3, r3, r4
; CHECK: cntlzw r3, r3
; CHECK: srwi r3, r3, 5
; CHECK: xori r3, r3, 1
; CHECK: neg r3, r3
; CHECK: stw r3, 0(r4)
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, %b
@ -93,10 +101,12 @@ entry:
define void @test_inesi_z_store(i32 signext %a) {
; CHECK-LABEL: test_inesi_z_store:
; CHECK: cntlzw r3, r3
; CHECK: srwi r3, r3, 5
; CHECK: xori r3, r3, 1
; CHECK: stw r3, 0(r4)
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stw r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, 0
@ -107,11 +117,13 @@ entry:
define void @test_inesi_sext_z_store(i32 signext %a) {
; CHECK-LABEL: test_inesi_sext_z_store:
; CHECK: cntlzw r3, r3
; CHECK: srwi r3, r3, 5
; CHECK: xori r3, r3, 1
; CHECK: neg r3, r3
; CHECK: stw r3, 0(r4)
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stw r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, 0

24
test/CodeGen/PowerPC/testComparesinesll.ll
View File

@ -61,12 +61,11 @@ entry:
define void @test_inesll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_inesll_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: addic r5, r3, -1
; CHECK-NEXT: subfe r3, r5, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: addic r4, r3, -1
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
@ -78,12 +77,11 @@ entry:
define void @test_inesll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_inesll_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
@ -95,11 +93,10 @@ entry:
define void @test_inesll_z_store(i64 %a) {
; CHECK-LABEL: test_inesll_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: addic r5, r3, -1
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: subfe r3, r5, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
@ -111,11 +108,10 @@ entry:
define void @test_inesll_sext_z_store(i64 %a) {
; CHECK-LABEL: test_inesll_sext_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0

62
test/CodeGen/PowerPC/testComparesiness.ll
View File

@ -1,16 +1,17 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i16 0, align 2
define signext i32 @test_iness(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iness:
; CHECK: xor r3, r3, r4
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
@ -23,7 +24,8 @@ entry:
define signext i32 @test_iness_sext(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iness_sext:
; CHECK: xor r3, r3, r4
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
@ -37,7 +39,8 @@ entry:
define signext i32 @test_iness_z(i16 signext %a) {
; CHECK-LABEL: test_iness_z:
; CHECK: cntlzw r3, r3
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
@ -49,7 +52,8 @@ entry:
define signext i32 @test_iness_sext_z(i16 signext %a) {
; CHECK-LABEL: test_iness_sext_z:
; CHECK: cntlzw r3, r3
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
@ -62,11 +66,13 @@ entry:
define void @test_iness_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iness_store:
; CHECK: xor r3, r3, r4
; CHECK: cntlzw r3, r3
; CHECK: srwi r3, r3, 5
; CHECK: xori r3, r3, 1
; CHECK: sth r3, 0(r4)
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, %b
@ -77,12 +83,14 @@ entry:
define void @test_iness_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iness_sext_store:
; CHECK: xor r3, r3, r4
; CHECK: cntlzw r3, r3
; CHECK: srwi r3, r3, 5
; CHECK: xori r3, r3, 1
; CHECK: neg r3, r3
; CHECK: sth r3, 0(r4)
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, %b
@ -93,10 +101,12 @@ entry:
define void @test_iness_z_store(i16 signext %a) {
; CHECK-LABEL: test_iness_z_store:
; CHECK: cntlzw r3, r3
; CHECK: srwi r3, r3, 5
; CHECK: xori r3, r3, 1
; CHECK: sth r3, 0(r4)
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sth r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, 0
@ -107,11 +117,13 @@ entry:
define void @test_iness_sext_z_store(i16 signext %a) {
; CHECK-LABEL: test_iness_sext_z_store:
; CHECK: cntlzw r3, r3
; CHECK: srwi r3, r3, 5
; CHECK: xori r3, r3, 1
; CHECK: neg r3, r3
; CHECK: sth r3, 0(r4)
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: sth r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, 0

20
test/CodeGen/PowerPC/testComparesineuc.ll
View File

@ -66,13 +66,12 @@ entry:
define void @test_ineuc_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_ineuc_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, %b
@ -85,13 +84,12 @@ define void @test_ineuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_ineuc_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, %b
@ -103,12 +101,11 @@ entry:
define void @test_ineuc_z_store(i8 zeroext %a) {
; CHECK-LABEL: test_ineuc_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: stb r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, 0
@ -120,13 +117,12 @@ entry:
define void @test_ineuc_sext_z_store(i8 zeroext %a) {
; CHECK-LABEL: test_ineuc_sext_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: stb r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, 0

62
test/CodeGen/PowerPC/testComparesineui.ll
View File

@ -1,16 +1,17 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i32 0, align 4
define signext i32 @test_ineui(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_ineui:
; CHECK: xor r3, r3, r4
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
@ -23,7 +24,8 @@ entry:
define signext i32 @test_ineui_sext(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_ineui_sext:
; CHECK: xor r3, r3, r4
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
@ -37,7 +39,8 @@ entry:
define signext i32 @test_ineui_z(i32 zeroext %a) {
; CHECK-LABEL: test_ineui_z:
; CHECK: cntlzw r3, r3
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
@ -49,7 +52,8 @@ entry:
define signext i32 @test_ineui_sext_z(i32 zeroext %a) {
; CHECK-LABEL: test_ineui_sext_z:
; CHECK: cntlzw r3, r3
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
@ -62,11 +66,13 @@ entry:
define void @test_ineui_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_ineui_store:
; CHECK: xor r3, r3, r4
; CHECK: cntlzw r3, r3
; CHECK: srwi r3, r3, 5
; CHECK: xori r3, r3, 1
; CHECK: stw r3, 0(r4)
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, %b
@ -77,12 +83,14 @@ entry:
define void @test_ineui_sext_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_ineui_sext_store:
; CHECK: xor r3, r3, r4
; CHECK: cntlzw r3, r3
; CHECK: srwi r3, r3, 5
; CHECK: xori r3, r3, 1
; CHECK: neg r3, r3
; CHECK: stw r3, 0(r4)
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, %b
@ -93,10 +101,12 @@ entry:
define void @test_ineui_z_store(i32 zeroext %a) {
; CHECK-LABEL: test_ineui_z_store:
; CHECK: cntlzw r3, r3
; CHECK: srwi r3, r3, 5
; CHECK: xori r3, r3, 1
; CHECK: stw r3, 0(r4)
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stw r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, 0
@ -107,11 +117,13 @@ entry:
define void @test_ineui_sext_z_store(i32 zeroext %a) {
; CHECK-LABEL: test_ineui_sext_z_store:
; CHECK: cntlzw r3, r3
; CHECK: srwi r3, r3, 5
; CHECK: xori r3, r3, 1
; CHECK: neg r3, r3
; CHECK: stw r3, 0(r4)
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stw r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, 0

24
test/CodeGen/PowerPC/testComparesineull.ll
View File

@ -61,12 +61,11 @@ entry:
define void @test_ineull_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_ineull_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: addic r5, r3, -1
; CHECK-NEXT: subfe r3, r5, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: addic r4, r3, -1
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
@ -78,12 +77,11 @@ entry:
define void @test_ineull_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_ineull_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
@ -95,11 +93,10 @@ entry:
define void @test_ineull_z_store(i64 %a) {
; CHECK-LABEL: test_ineull_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: addic r5, r3, -1
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: subfe r3, r5, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
@ -111,11 +108,10 @@ entry:
define void @test_ineull_sext_z_store(i64 %a) {
; CHECK-LABEL: test_ineull_sext_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0

20
test/CodeGen/PowerPC/testComparesineus.ll
View File

@ -67,13 +67,12 @@ entry:
define void @test_ineus_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_ineus_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, %b
@ -86,13 +85,12 @@ define void @test_ineus_sext_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_ineus_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, %b
@ -104,12 +102,11 @@ entry:
define void @test_ineus_z_store(i16 zeroext %a) {
; CHECK-LABEL: test_ineus_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: sth r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, 0
@ -121,13 +118,12 @@ entry:
define void @test_ineus_sext_z_store(i16 zeroext %a) {
; CHECK-LABEL: test_ineus_sext_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: sth r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, 0

20
test/CodeGen/PowerPC/testCompareslleqsc.ll
View File

@ -69,12 +69,11 @@ entry:
define void @test_lleqsc_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_lleqsc_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, %b
@ -87,13 +86,12 @@ entry:
define void @test_lleqsc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_lleqsc_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, %b
@ -106,11 +104,10 @@ entry:
define void @test_lleqsc_z_store(i8 signext %a) {
; CHECK-LABEL: test_lleqsc_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: stb r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, 0
@ -123,12 +120,11 @@ entry:
define void @test_lleqsc_sext_z_store(i8 signext %a) {
; CHECK-LABEL: test_lleqsc_sext_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: stb r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, 0

20
test/CodeGen/PowerPC/testCompareslleqsi.ll
View File

@ -68,12 +68,11 @@ entry:
define void @test_lleqsi_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_lleqsi_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, %b
@ -86,13 +85,12 @@ entry:
define void @test_lleqsi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_lleqsi_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, %b
@ -105,11 +103,10 @@ entry:
define void @test_lleqsi_z_store(i32 signext %a) {
; CHECK-LABEL: test_lleqsi_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: stw r3, glob@toc@l(r4)
; CHECK-NEXT: blr
; CHECKNEXT: blr
entry:
@ -123,12 +120,11 @@ entry:
define void @test_lleqsi_sext_z_store(i32 signext %a) {
; CHECK-LABEL: test_lleqsi_sext_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: stw r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, 0

20
test/CodeGen/PowerPC/testCompareslleqsll.ll
View File

@ -66,12 +66,11 @@ entry:
define void @test_lleqsll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_lleqsll_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
@ -84,12 +83,11 @@ entry:
define void @test_lleqsll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_lleqsll_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
@ -102,11 +100,10 @@ entry:
define void @test_lleqsll_z_store(i64 %a) {
; CHECK-LABEL: test_lleqsll_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, 0
@ -119,11 +116,10 @@ entry:
define void @test_lleqsll_sext_z_store(i64 %a) {
; CHECK-LABEL: test_lleqsll_sext_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, 0

20
test/CodeGen/PowerPC/testCompareslleqss.ll
View File

@ -68,12 +68,11 @@ entry:
define void @test_lleqss_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_lleqss_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, %b
@ -86,13 +85,12 @@ entry:
define void @test_lleqss_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_lleqss_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, %b
@ -105,11 +103,10 @@ entry:
define void @test_lleqss_z_store(i16 signext %a) {
; CHECK-LABEL: test_lleqss_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: sth r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, 0
@ -122,12 +119,11 @@ entry:
define void @test_lleqss_sext_z_store(i16 signext %a) {
; CHECK-LABEL: test_lleqss_sext_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: sth r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, 0

20
test/CodeGen/PowerPC/testComparesllequc.ll
View File

@ -68,12 +68,11 @@ entry:
define void @test_llequc_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_llequc_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, %b
@ -86,13 +85,12 @@ entry:
define void @test_llequc_sext_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_llequc_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, %b
@ -105,11 +103,10 @@ entry:
define void @test_llequc_z_store(i8 zeroext %a) {
; CHECK-LABEL: test_llequc_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: stb r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, 0
@ -122,12 +119,11 @@ entry:
define void @test_llequc_sext_z_store(i8 zeroext %a) {
; CHECK-LABEL: test_llequc_sext_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: stb r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, 0

20
test/CodeGen/PowerPC/testComparesllequi.ll
View File

@ -68,12 +68,11 @@ entry:
define void @test_llequi_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_llequi_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, %b
@ -86,13 +85,12 @@ entry:
define void @test_llequi_sext_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_llequi_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, %b
@ -105,11 +103,10 @@ entry:
define void @test_llequi_z_store(i32 zeroext %a) {
; CHECK-LABEL: test_llequi_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: stw r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, 0
@ -122,12 +119,11 @@ entry:
define void @test_llequi_sext_z_store(i32 zeroext %a) {
; CHECK-LABEL: test_llequi_sext_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: stw r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, 0

20
test/CodeGen/PowerPC/testComparesllequll.ll
View File

@ -66,12 +66,11 @@ entry:
define void @test_llequll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_llequll_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
@ -84,12 +83,11 @@ entry:
define void @test_llequll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_llequll_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
@ -102,11 +100,10 @@ entry:
define void @test_llequll_z_store(i64 %a) {
; CHECK-LABEL: test_llequll_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, 0
@ -119,11 +116,10 @@ entry:
define void @test_llequll_sext_z_store(i64 %a) {
; CHECK-LABEL: test_llequll_sext_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, 0

20
test/CodeGen/PowerPC/testComparesllequs.ll
View File

@ -68,12 +68,11 @@ entry:
define void @test_llequs_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_llequs_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, %b
@ -86,13 +85,12 @@ entry:
define void @test_llequs_sext_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_llequs_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, %b
@ -105,11 +103,10 @@ entry:
define void @test_llequs_z_store(i16 zeroext %a) {
; CHECK-LABEL: test_llequs_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: sth r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, 0
@ -122,12 +119,11 @@ entry:
define void @test_llequs_sext_z_store(i16 zeroext %a) {
; CHECK-LABEL: test_llequs_sext_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: sth r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, 0

10
test/CodeGen/PowerPC/testComparesllgesc.ll
View File

@ -36,12 +36,11 @@ entry:
define void @test_llgesc_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_llgesc_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i8 %a, %b
@ -53,12 +52,11 @@ entry:
define void @test_llgesc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_llgesc_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i8 %a, %b

10
test/CodeGen/PowerPC/testComparesllgesi.ll
View File

@ -36,12 +36,11 @@ entry:
define void @test_llgesi_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_llgesi_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i32 %a, %b
@ -53,12 +52,11 @@ entry:
define void @test_llgesi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_llgesi_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i32 %a, %b

28
test/CodeGen/PowerPC/testComparesllgesll.ll
View File

@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i64 0, align 8
define i64 @test_llgesll(i64 %a, i64 %b) {
@ -63,11 +63,12 @@ entry:
define void @test_llgesll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_llgesll_store:
; CHECK: # %bb.0: # %entry
; CHECK: sradi r6, r3, 63
; CHECK: subfc r3, r4, r3
; CHECK: rldicl r3, r4, 1, 63
; CHECK: adde r3, r6, r3
; CHECK: std r3,
; CHECK-NEXT: sradi r6, r3, 63
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: subfc r3, r4, r3
; CHECK-NEXT: rldicl r3, r4, 1, 63
; CHECK-NEXT: adde r3, r6, r3
; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i64 %a, %b
@ -80,13 +81,12 @@ define void @test_llgesll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_llgesll_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r6, r3, 63
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: subfc r3, r4, r3
; CHECK-NEXT: rldicl r3, r4, 1, 63
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: adde r3, r6, r3
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i64 %a, %b
@ -98,11 +98,10 @@ entry:
define void @test_llgesll_z_store(i64 %a) {
; CHECK-LABEL: test_llgesll_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: not r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i64 %a, -1
@ -114,11 +113,10 @@ entry:
define void @test_llgesll_sext_z_store(i64 %a) {
; CHECK-LABEL: test_llgesll_sext_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: not r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i64 %a, -1

10
test/CodeGen/PowerPC/testComparesllgess.ll
View File

@ -36,12 +36,11 @@ entry:
define void @test_llgess_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llgess_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i16 %a, %b
@ -53,12 +52,11 @@ entry:
define void @test_llgess_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llgess_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i16 %a, %b

4
test/CodeGen/PowerPC/testComparesllgtsll.ll
View File

@ -1,7 +1,7 @@
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl

4
test/CodeGen/PowerPC/testComparesllgtuc.ll
View File

@ -1,7 +1,7 @@
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl

4
test/CodeGen/PowerPC/testComparesllgtui.ll
View File

@ -1,7 +1,7 @@
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl

4
test/CodeGen/PowerPC/testComparesllgtus.ll
View File

@ -1,7 +1,7 @@
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl

10
test/CodeGen/PowerPC/testCompareslllesc.ll
View File

@ -37,12 +37,11 @@ entry:
define void @test_lllesc_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_lllesc_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i8 %a, %b
@ -54,12 +53,11 @@ entry:
define void @test_lllesc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_lllesc_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i8 %a, %b

10
test/CodeGen/PowerPC/testCompareslllesi.ll
View File

@ -37,12 +37,11 @@ entry:
define void @test_lllesi_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_lllesi_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i32 %a, %b
@ -54,12 +53,11 @@ entry:
define void @test_lllesi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_lllesi_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i32 %a, %b

20
test/CodeGen/PowerPC/testCompareslllesll.ll
View File

@ -70,13 +70,12 @@ entry:
define void @test_lllesll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_lllesll_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sradi r6, r4, 63
; CHECK-NEXT: ld r5, .LC0@toc@l(r5)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: subfc r4, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: adde r3, r6, r3
; CHECK-NEXT: std r3, 0(r5)
; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i64 %a, %b
@ -90,13 +89,12 @@ define void @test_lllesll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_lllesll_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r6, r4, 63
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: subfc r4, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: adde r3, r6, r3
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i64 %a, %b
@ -109,12 +107,11 @@ entry:
define void @test_lllesll_z_store(i64 %a) {
; CHECK-LABEL: test_lllesll_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: addi r5, r3, -1
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: or r3, r5, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i64 %a, 1
@ -127,12 +124,11 @@ entry:
define void @test_lllesll_sext_z_store(i64 %a) {
; CHECK-LABEL: test_lllesll_sext_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: addi r5, r3, -1
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: or r3, r5, r3
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i64 %a, 1

10
test/CodeGen/PowerPC/testComparesllless.ll
View File

@ -37,12 +37,11 @@ entry:
define void @test_llless_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llless_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i16 %a, %b
@ -54,12 +53,11 @@ entry:
define void @test_llless_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llless_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i16 %a, %b

4
test/CodeGen/PowerPC/testComparesllltui.ll
View File

@ -1,7 +1,7 @@
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: llc --relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl

24
test/CodeGen/PowerPC/testComparesllnesll.ll
View File

@ -61,12 +61,11 @@ entry:
define void @test_llnesll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_llnesll_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: addic r5, r3, -1
; CHECK-NEXT: subfe r3, r5, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: addic r4, r3, -1
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
@ -78,12 +77,11 @@ entry:
define void @test_llnesll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_llnesll_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
@ -95,11 +93,10 @@ entry:
define void @test_llnesll_z_store(i64 %a) {
; CHECK-LABEL: test_llnesll_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: addic r5, r3, -1
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: subfe r3, r5, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
@ -111,11 +108,10 @@ entry:
define void @test_llnesll_sext_z_store(i64 %a) {
; CHECK-LABEL: test_llnesll_sext_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0

24
test/CodeGen/PowerPC/testComparesllneull.ll
View File

@ -61,12 +61,11 @@ entry:
define void @test_llneull_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_llneull_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: addic r5, r3, -1
; CHECK-NEXT: subfe r3, r5, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: addic r4, r3, -1
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
@ -78,12 +77,11 @@ entry:
define void @test_llneull_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_llneull_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
@ -95,11 +93,10 @@ entry:
define void @test_llneull_z_store(i64 %a) {
; CHECK-LABEL: test_llneull_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: addic r5, r3, -1
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: subfe r3, r5, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
@ -111,11 +108,10 @@ entry:
define void @test_llneull_sext_z_store(i64 %a) {
; CHECK-LABEL: test_llneull_sext_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0

4
test/CodeGen/PowerPC/toc-float.ll
View File

@ -1,5 +1,5 @@
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 <%s | FileCheck -check-prefix=CHECK-P9 %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 <%s | FileCheck -check-prefix=CHECK-P8 %s
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 <%s | FileCheck -check-prefix=CHECK-P9 %s
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 <%s | FileCheck -check-prefix=CHECK-P8 %s
; As the constant could be represented as float, a float is
; loaded from constant pool.

4
test/CodeGen/PowerPC/vsx_scalar_ld_st.ll
View File

@ -1,6 +1,6 @@
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu \
; RUN: llc -relocation-model=pic -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr8 -mattr=-direct-move | FileCheck %s
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: llc -relocation-model=pic -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr8 -mattr=-direct-move | FileCheck %s
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr9 -mattr=-direct-move | FileCheck %s -check-prefix=CHECK-P9

2
test/CodeGen/PowerPC/xray-tail-call-sled.ll
View File

@ -1,4 +1,4 @@
; RUN: llc -filetype=asm -o - -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
; RUN: llc -filetype=asm -relocation-model=pic -o - -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
define i32 @callee() nounwind noinline uwtable "function-instrument"="xray-always" {
; CHECK-LABEL: .Ltmp0: