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[Hexagon] Adding orand, bitsplit reg/reg, and modwrap instructions.

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llvm-svn: 225197
This commit is contained in:
Colin LeMahieu 2015-01-05 20:04:40 +00:00
parent 21f185051b
commit e42756883b
3 changed files with 63 additions and 0 deletions
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57
lib/Target/Hexagon/HexagonInstrInfoV4.td
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@ -1762,6 +1762,63 @@ def A4_round_ri : T_S2op_2_ii <"round", 0b111, 0b100>;
let Defs = [USR_OVF], isCodeGenOnly = 0 in
def A4_round_ri_sat : T_S2op_2_ii <"round", 0b111, 0b110, 1>;
// Logical-logical words.
// Compound or-and -- Rx=or(Ru,and(Rx,#s10))
let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1, opExtentBits = 10,
opExtendable = 3, isCodeGenOnly = 0 in
def S4_or_andix:
ALU64Inst<(outs IntRegs:$Rx),
(ins IntRegs:$Ru, IntRegs:$_src_, s10Ext:$s10),
"$Rx = or($Ru, and($_src_, #$s10))" ,
[(set (i32 IntRegs:$Rx),
(or (i32 IntRegs:$Ru), (and (i32 IntRegs:$_src_), s10ExtPred:$s10)))] ,
"$_src_ = $Rx", ALU64_tc_2_SLOT23> {
bits<5> Rx;
bits<5> Ru;
bits<10> s10;
let IClass = 0b1101;
let Inst{27-22} = 0b101001;
let Inst{20-16} = Rx;
let Inst{21} = s10{9};
let Inst{13-5} = s10{8-0};
let Inst{4-0} = Ru;
}
// Miscellaneous ALU64 instructions.
//
let hasNewValue = 1, hasSideEffects = 0, isCodeGenOnly = 0 in
def A4_modwrapu: ALU64Inst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
"$Rd = modwrap($Rs, $Rt)", [], "", ALU64_tc_2_SLOT23> {
bits<5> Rd;
bits<5> Rs;
bits<5> Rt;
let IClass = 0b1101;
let Inst{27-21} = 0b0011111;
let Inst{20-16} = Rs;
let Inst{12-8} = Rt;
let Inst{7-5} = 0b111;
let Inst{4-0} = Rd;
}
let hasSideEffects = 0, isCodeGenOnly = 0 in
def A4_bitsplit: ALU64Inst<(outs DoubleRegs:$Rd),
(ins IntRegs:$Rs, IntRegs:$Rt),
"$Rd = bitsplit($Rs, $Rt)", [], "", ALU64_tc_1_SLOT23> {
bits<5> Rd;
bits<5> Rs;
bits<5> Rt;
let IClass = 0b1101;
let Inst{27-24} = 0b0100;
let Inst{21} = 0b1;
let Inst{20-16} = Rs;
let Inst{12-8} = Rt;
let Inst{4-0} = Rd;
}
// Add and accumulate.
// Rd=add(Rs,add(Ru,#s6))
let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 6,

4
test/MC/Disassembler/Hexagon/xtype_alu.txt
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@ -64,6 +64,8 @@
# CHECK: r17:16 = or(r21:20, ~r31:30)
0x10 0xde 0x94 0xca
# CHECK: r17:16 ^= xor(r21:20, r31:30)
0xf5 0xc3 0x51 0xda
# CHECK: r17 = or(r21, and(r17, #31))
0x71 0xdf 0x95 0xef
# CHECK: r17 ^= xor(r21, r31)
0x11 0xdf 0xd5 0xd5
@ -82,6 +84,8 @@
# CHECK: r17:16 = min(r21:20, r31:30)
0xf0 0xd4 0xbe 0xd3
# CHECK: r17:16 = minu(r21:20, r31:30)
0xf1 0xdf 0xf5 0xd3
# CHECK: r17 = modwrap(r21, r31)
0xb0 0xc0 0x94 0x80
# CHECK: r17:16 = neg(r21:20)
0xd1 0xc0 0x95 0x8c

2
test/MC/Disassembler/Hexagon/xtype_bit.txt
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@ -66,6 +66,8 @@
# CHECK: r17 = togglebit(r21, r31)
0x90 0xdf 0xd5 0x88
# CHECK: r17:16 = bitsplit(r21, #31)
0x10 0xdf 0x35 0xd4
# CHECK: r17:16 = bitsplit(r21, r31)
0xf1 0xcd 0x15 0x87
# CHECK: r17 = tableidxb(r21, #7, #13):raw
0xf1 0xcd 0x55 0x87