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[LV] Add test which sinks a load a across an aliasing store.
This commit is contained in:
Florian Hahn
parent
411894471f
commit
e42fe52d55
@ -623,3 +623,139 @@ for.inc:
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for.end:
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ret void
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}
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define void @minimal_bit_widths_with_aliasing_store(i1 %c, i8* %ptr) {
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; UNROLL-LABEL: @minimal_bit_widths_with_aliasing_store(
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; UNROLL-NEXT: entry:
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; UNROLL-NEXT: br label [[FOR_BODY:%.*]]
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; UNROLL: for.body:
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; UNROLL-NEXT: [[TMP0:%.*]] = phi i64 [ [[TMP6:%.*]], [[FOR_INC:%.*]] ], [ 0, [[ENTRY:%.*]] ]
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; UNROLL-NEXT: [[TMP1:%.*]] = phi i64 [ [[TMP7:%.*]], [[FOR_INC]] ], [ 0, [[ENTRY]] ]
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; UNROLL-NEXT: [[TMP2:%.*]] = getelementptr i8, i8* [[PTR:%.*]], i64 [[TMP0]]
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; UNROLL-NEXT: [[TMP3:%.*]] = load i8, i8* [[TMP2]], align 1
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; UNROLL-NEXT: store i8 0, i8* [[TMP2]], align 1
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; UNROLL-NEXT: br i1 [[C:%.*]], label [[IF_THEN:%.*]], label [[FOR_INC]]
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; UNROLL: if.then:
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; UNROLL-NEXT: [[TMP4:%.*]] = zext i8 [[TMP3]] to i32
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; UNROLL-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i8
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; UNROLL-NEXT: store i8 [[TMP5]], i8* [[TMP2]], align 1
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; UNROLL-NEXT: br label [[FOR_INC]]
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; UNROLL: for.inc:
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; UNROLL-NEXT: [[TMP6]] = add nuw nsw i64 [[TMP0]], 1
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; UNROLL-NEXT: [[TMP7]] = add i64 [[TMP1]], -1
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; UNROLL-NEXT: [[TMP8:%.*]] = icmp eq i64 [[TMP7]], 0
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; UNROLL-NEXT: br i1 [[TMP8]], label [[FOR_END:%.*]], label [[FOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
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; UNROLL: for.end:
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; UNROLL-NEXT: ret void
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;
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; UNROLL-NOSIMPLIFY-LABEL: @minimal_bit_widths_with_aliasing_store(
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; UNROLL-NOSIMPLIFY-NEXT: entry:
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; UNROLL-NOSIMPLIFY-NEXT: br i1 true, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
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; UNROLL-NOSIMPLIFY: vector.ph:
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; UNROLL-NOSIMPLIFY-NEXT: br label [[VECTOR_BODY:%.*]]
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; UNROLL-NOSIMPLIFY: vector.body:
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; UNROLL-NOSIMPLIFY-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE6:%.*]] ]
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; UNROLL-NOSIMPLIFY-NEXT: [[INDUCTION:%.*]] = add i64 [[INDEX]], 0
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; UNROLL-NOSIMPLIFY-NEXT: [[INDUCTION2:%.*]] = add i64 [[INDEX]], 1
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; UNROLL-NOSIMPLIFY-NEXT: [[OFFSET_IDX:%.*]] = sub i64 0, [[INDEX]]
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; UNROLL-NOSIMPLIFY-NEXT: [[INDUCTION3:%.*]] = add i64 [[OFFSET_IDX]], 0
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; UNROLL-NOSIMPLIFY-NEXT: [[INDUCTION4:%.*]] = add i64 [[OFFSET_IDX]], -1
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; UNROLL-NOSIMPLIFY-NEXT: [[TMP0:%.*]] = getelementptr i8, i8* [[PTR:%.*]], i64 [[INDUCTION]]
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; UNROLL-NOSIMPLIFY-NEXT: [[TMP1:%.*]] = getelementptr i8, i8* [[PTR]], i64 [[INDUCTION2]]
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; UNROLL-NOSIMPLIFY-NEXT: store i8 0, i8* [[TMP0]], align 1
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; UNROLL-NOSIMPLIFY-NEXT: store i8 0, i8* [[TMP1]], align 1
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; UNROLL-NOSIMPLIFY-NEXT: br i1 [[C:%.*]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]]
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; UNROLL-NOSIMPLIFY: pred.store.if:
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; UNROLL-NOSIMPLIFY-NEXT: [[TMP2:%.*]] = load i8, i8* [[TMP0]], align 1
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; UNROLL-NOSIMPLIFY-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i32
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; UNROLL-NOSIMPLIFY-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i8
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; UNROLL-NOSIMPLIFY-NEXT: store i8 [[TMP4]], i8* [[TMP0]], align 1
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; UNROLL-NOSIMPLIFY-NEXT: br label [[PRED_STORE_CONTINUE]]
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; UNROLL-NOSIMPLIFY: pred.store.continue:
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; UNROLL-NOSIMPLIFY-NEXT: br i1 [[C]], label [[PRED_STORE_IF5:%.*]], label [[PRED_STORE_CONTINUE6]]
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; UNROLL-NOSIMPLIFY: pred.store.if5:
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; UNROLL-NOSIMPLIFY-NEXT: [[TMP5:%.*]] = load i8, i8* [[TMP1]], align 1
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; UNROLL-NOSIMPLIFY-NEXT: [[TMP6:%.*]] = zext i8 [[TMP5]] to i32
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; UNROLL-NOSIMPLIFY-NEXT: [[TMP7:%.*]] = trunc i32 [[TMP6]] to i8
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; UNROLL-NOSIMPLIFY-NEXT: store i8 [[TMP7]], i8* [[TMP1]], align 1
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; UNROLL-NOSIMPLIFY-NEXT: br label [[PRED_STORE_CONTINUE6]]
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; UNROLL-NOSIMPLIFY: pred.store.continue6:
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; UNROLL-NOSIMPLIFY-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 2
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; UNROLL-NOSIMPLIFY-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], 0
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; UNROLL-NOSIMPLIFY-NEXT: br i1 [[TMP8]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]
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; UNROLL-NOSIMPLIFY: middle.block:
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; UNROLL-NOSIMPLIFY-NEXT: [[CMP_N:%.*]] = icmp eq i64 0, 0
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; UNROLL-NOSIMPLIFY-NEXT: br i1 [[CMP_N]], label [[FOR_END:%.*]], label [[SCALAR_PH]]
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; UNROLL-NOSIMPLIFY: scalar.ph:
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; UNROLL-NOSIMPLIFY-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 0, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]
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; UNROLL-NOSIMPLIFY-NEXT: [[BC_RESUME_VAL1:%.*]] = phi i64 [ 0, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ]
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; UNROLL-NOSIMPLIFY-NEXT: br label [[FOR_BODY:%.*]]
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; UNROLL-NOSIMPLIFY: for.body:
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; UNROLL-NOSIMPLIFY-NEXT: [[TMP0:%.*]] = phi i64 [ [[TMP6:%.*]], [[FOR_INC:%.*]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ]
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; UNROLL-NOSIMPLIFY-NEXT: [[TMP1:%.*]] = phi i64 [ [[TMP7:%.*]], [[FOR_INC]] ], [ [[BC_RESUME_VAL1]], [[SCALAR_PH]] ]
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; UNROLL-NOSIMPLIFY-NEXT: [[TMP2:%.*]] = getelementptr i8, i8* [[PTR]], i64 [[TMP0]]
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; UNROLL-NOSIMPLIFY-NEXT: [[TMP3:%.*]] = load i8, i8* [[TMP2]], align 1
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; UNROLL-NOSIMPLIFY-NEXT: store i8 0, i8* [[TMP2]], align 1
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; UNROLL-NOSIMPLIFY-NEXT: br i1 [[C]], label [[IF_THEN:%.*]], label [[FOR_INC]]
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; UNROLL-NOSIMPLIFY: if.then:
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; UNROLL-NOSIMPLIFY-NEXT: [[TMP4:%.*]] = zext i8 [[TMP3]] to i32
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; UNROLL-NOSIMPLIFY-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i8
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; UNROLL-NOSIMPLIFY-NEXT: store i8 [[TMP5]], i8* [[TMP2]], align 1
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; UNROLL-NOSIMPLIFY-NEXT: br label [[FOR_INC]]
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; UNROLL-NOSIMPLIFY: for.inc:
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; UNROLL-NOSIMPLIFY-NEXT: [[TMP6]] = add nuw nsw i64 [[TMP0]], 1
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; UNROLL-NOSIMPLIFY-NEXT: [[TMP7]] = add i64 [[TMP1]], -1
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; UNROLL-NOSIMPLIFY-NEXT: [[TMP8:%.*]] = icmp eq i64 [[TMP7]], 0
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; UNROLL-NOSIMPLIFY-NEXT: br i1 [[TMP8]], label [[FOR_END]], label [[FOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
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; UNROLL-NOSIMPLIFY: for.end:
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; UNROLL-NOSIMPLIFY-NEXT: ret void
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;
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; VEC-LABEL: @minimal_bit_widths_with_aliasing_store(
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; VEC-NEXT: entry:
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; VEC-NEXT: br label [[FOR_BODY:%.*]]
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; VEC: for.body:
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; VEC-NEXT: [[TMP0:%.*]] = phi i64 [ [[TMP6:%.*]], [[FOR_INC:%.*]] ], [ 0, [[ENTRY:%.*]] ]
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; VEC-NEXT: [[TMP1:%.*]] = phi i64 [ [[TMP7:%.*]], [[FOR_INC]] ], [ 0, [[ENTRY]] ]
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; VEC-NEXT: [[TMP2:%.*]] = getelementptr i8, i8* [[PTR:%.*]], i64 [[TMP0]]
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; VEC-NEXT: [[TMP3:%.*]] = load i8, i8* [[TMP2]], align 1
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; VEC-NEXT: store i8 0, i8* [[TMP2]], align 1
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; VEC-NEXT: br i1 [[C:%.*]], label [[IF_THEN:%.*]], label [[FOR_INC]]
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; VEC: if.then:
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; VEC-NEXT: [[TMP4:%.*]] = zext i8 [[TMP3]] to i32
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; VEC-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i8
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; VEC-NEXT: store i8 [[TMP5]], i8* [[TMP2]], align 1
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; VEC-NEXT: br label [[FOR_INC]]
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; VEC: for.inc:
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; VEC-NEXT: [[TMP6]] = add nuw nsw i64 [[TMP0]], 1
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; VEC-NEXT: [[TMP7]] = add i64 [[TMP1]], -1
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; VEC-NEXT: [[TMP8:%.*]] = icmp eq i64 [[TMP7]], 0
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; VEC-NEXT: br i1 [[TMP8]], label [[FOR_END:%.*]], label [[FOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]
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; VEC: for.end:
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; VEC-NEXT: ret void
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;
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entry:
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br label %for.body
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for.body:
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%tmp0 = phi i64 [ %tmp6, %for.inc ], [ 0, %entry ]
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%tmp1 = phi i64 [ %tmp7, %for.inc ], [ 0, %entry ]
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%tmp2 = getelementptr i8, i8* %ptr, i64 %tmp0
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%tmp3 = load i8, i8* %tmp2, align 1
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store i8 0, i8* %tmp2
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br i1 %c, label %if.then, label %for.inc
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if.then:
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%tmp4 = zext i8 %tmp3 to i32
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%tmp5 = trunc i32 %tmp4 to i8
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store i8 %tmp5, i8* %tmp2, align 1
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br label %for.inc
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for.inc:
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%tmp6 = add nuw nsw i64 %tmp0, 1
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%tmp7 = add i64 %tmp1, -1
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%tmp8 = icmp eq i64 %tmp7, 0
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br i1 %tmp8, label %for.end, label %for.body
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for.end:
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ret void
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}
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