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Fix clang -Wimplicit-fallthrough warnings across llvm, NFC

Browse Source 
This patch should not introduce any behavior changes. It consists of
mostly one of two changes:
1. Replacing fall through comments with the LLVM_FALLTHROUGH macro
2. Inserting 'break' before falling through into a case block consisting
   of only 'break'.

We were already using this warning with GCC, but its warning behaves
slightly differently. In this patch, the following differences are
relevant:
1. GCC recognizes comments that say "fall through" as annotations, clang
   doesn't
2. GCC doesn't warn on "case N: foo(); default: break;", clang does
3. GCC doesn't warn when the case contains a switch, but falls through
   the outer case.

I will enable the warning separately in a follow-up patch so that it can
be cleanly reverted if necessary.

Reviewers: alexfh, rsmith, lattner, rtrieu, EricWF, bollu

Differential Revision: https://reviews.llvm.org/D53950

llvm-svn: 345882
This commit is contained in:
Reid Kleckner 2018-11-01 19:54:45 +00:00
parent b6616fa5de
commit e4344b4fba
20 changed files with 23 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
include/llvm/Demangle/ItaniumDemangle.h
View File

@ -2807,6 +2807,7 @@ AbstractManglingParser<Derived, Alloc>::parseCtorDtorName(Node *&SoFar,
SoFar = make<ExpandedSpecialSubstitution>(SSK);
if (!SoFar)
return nullptr;
break;
default:
break;
}

1
lib/Analysis/InlineCost.cpp
View File

@ -720,6 +720,7 @@ bool CallAnalyzer::visitCastInst(CastInst &I) {
case Instruction::FPToSI:
if (TTI.getFPOpCost(I.getType()) == TargetTransformInfo::TCC_Expensive)
Cost += InlineConstants::CallPenalty;
break;
default:
break;
}

1
lib/Demangle/MicrosoftDemangleNodes.cpp
View File

@ -558,6 +558,7 @@ void VariableSymbolNode::output(OutputStream &OS, OutputFlags Flags) const {
case StorageClass::PublicStatic:
case StorageClass::ProtectedStatic:
OS << "static ";
break;
default:
break;
}

2
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
View File

@ -351,7 +351,7 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
case AMDGPU::G_SHL:
if (isSALUMapping(MI))
return getDefaultMappingSOP(MI);
// Fall-through
LLVM_FALLTHROUGH;
case AMDGPU::G_FADD:
case AMDGPU::G_FPTOSI:

1
lib/Target/AMDGPU/R600MachineScheduler.cpp
View File

@ -236,6 +236,7 @@ R600SchedStrategy::AluKind R600SchedStrategy::getAluKind(SUnit *SU) const {
// MI will become a KILL, don't considers it in scheduling
return AluDiscarded;
}
break;
default:
break;
}

3
lib/Target/AMDGPU/SIISelLowering.cpp
View File

@ -5049,12 +5049,11 @@ SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
case Intrinsic::r600_read_tgid_z:
return getPreloadedValue(DAG, *MFI, VT,
AMDGPUFunctionArgInfo::WORKGROUP_ID_Z);
case Intrinsic::amdgcn_workitem_id_x: {
case Intrinsic::amdgcn_workitem_id_x:
case Intrinsic::r600_read_tidig_x:
return loadInputValue(DAG, &AMDGPU::VGPR_32RegClass, MVT::i32,
SDLoc(DAG.getEntryNode()),
MFI->getArgInfo().WorkItemIDX);
}
case Intrinsic::amdgcn_workitem_id_y:
case Intrinsic::r600_read_tidig_y:
return loadInputValue(DAG, &AMDGPU::VGPR_32RegClass, MVT::i32,

2
lib/Target/BPF/AsmParser/BPFAsmParser.cpp
View File

@ -357,8 +357,8 @@ BPFAsmParser::parseOperandAsOperator(OperandVector &Operands) {
case AsmToken::Plus: {
if (getLexer().peekTok().is(AsmToken::Integer))
return MatchOperand_NoMatch;
LLVM_FALLTHROUGH;
}
// Fall through.
case AsmToken::Equal:
case AsmToken::Greater:

1
lib/Target/Hexagon/HexagonConstExtenders.cpp
View File

@ -1208,6 +1208,7 @@ void HCE::recordExtender(MachineInstr &MI, unsigned OpNum) {
case Hexagon::S4_subaddi: // (__: ## - Rs<<0)
ED.Expr.Rs = MI.getOperand(OpNum+1);
ED.Expr.Neg = true;
break;
default: // (__: ## + __<<_)
break;
}

1
lib/Target/Hexagon/HexagonConstPropagation.cpp
View File

@ -2463,6 +2463,7 @@ APInt HexagonConstEvaluator::getCmpImm(unsigned Opc, unsigned OpX,
case Hexagon::A4_cmpheqi: // s8
case Hexagon::C4_cmpneqi: // s8
Signed = true;
break;
case Hexagon::A4_cmpbeqi: // u8
break;
case Hexagon::C2_cmpgtui: // u9

1
lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
View File

@ -1547,6 +1547,7 @@ bool HexagonDAGToDAGISel::keepsLowBits(const SDValue &Val, unsigned NumBits,
return true;
}
}
break;
}
default:
break;

1
lib/Target/Hexagon/HexagonMachineScheduler.cpp
View File

@ -105,6 +105,7 @@ bool VLIWResourceModel::isResourceAvailable(SUnit *SU, bool IsTop) {
default:
if (!ResourcesModel->canReserveResources(*SU->getInstr()))
return false;
break;
case TargetOpcode::EXTRACT_SUBREG:
case TargetOpcode::INSERT_SUBREG:
case TargetOpcode::SUBREG_TO_REG:

1
lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
View File

@ -1568,6 +1568,7 @@ bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
if (GlueAllocframeStore)
continue;
}
break;
default:
break;
}

4
lib/Target/Mips/AsmParser/MipsAsmParser.cpp
View File

@ -767,13 +767,13 @@ public:
~MipsOperand() override {
switch (Kind) {
case k_Immediate:
break;
case k_Memory:
delete Mem.Base;
break;
case k_RegList:
delete RegList.List;
break;
case k_Immediate:
case k_RegisterIndex:
case k_Token:
break;

1
lib/Target/Mips/MipsAsmPrinter.cpp
View File

@ -561,6 +561,7 @@ bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
O << '$' << MipsInstPrinter::getRegisterName(Reg);
return false;
}
break;
}
case 'w':
// Print MSA registers for the 'f' constraint

2
lib/Target/Mips/MipsSEISelDAGToDAG.cpp
View File

@ -244,7 +244,7 @@ void MipsSEDAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) {
MI.addOperand(MachineOperand::CreateReg(Mips::SP, false, true));
break;
}
// fallthrough
LLVM_FALLTHROUGH;
case Mips::BuildPairF64:
case Mips::ExtractElementF64:
if (Subtarget->isABI_FPXX() && !Subtarget->hasMTHC1())

2
lib/Target/PowerPC/PPCFastISel.cpp
View File

@ -903,7 +903,7 @@ bool PPCFastISel::PPCEmitCmp(const Value *SrcValue1, const Value *SrcValue2,
case MVT::i8:
case MVT::i16:
NeedsExt = true;
// Intentional fall-through.
LLVM_FALLTHROUGH;
case MVT::i32:
if (!UseImm)
CmpOpc = IsZExt ? PPC::CMPLW : PPC::CMPW;

4
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -3970,7 +3970,7 @@ SDValue PPCTargetLowering::LowerFormalArguments_64SVR4(
assert(ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 &&
"Invalid QPX parameter type");
/* fall through */
LLVM_FALLTHROUGH;
case MVT::v4f64:
case MVT::v4i1:
@ -6113,7 +6113,7 @@ SDValue PPCTargetLowering::LowerCall_64SVR4(
assert(Arg.getValueType().getSimpleVT().SimpleTy == MVT::v4f32 &&
"Invalid QPX parameter type");
/* fall through */
LLVM_FALLTHROUGH;
case MVT::v4f64:
case MVT::v4i1: {
bool IsF32 = Arg.getValueType().getSimpleVT().SimpleTy == MVT::v4f32;

4
lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
View File

@ -1308,7 +1308,7 @@ bool SystemZDAGToDAGISel::tryFoldLoadStoreIntoMemOperand(SDNode *Node) {
return false;
case SystemZISD::SSUBO:
NegateOperand = true;
/* fall through */
LLVM_FALLTHROUGH;
case SystemZISD::SADDO:
if (MemVT == MVT::i32)
NewOpc = SystemZ::ASI;
@ -1319,7 +1319,7 @@ bool SystemZDAGToDAGISel::tryFoldLoadStoreIntoMemOperand(SDNode *Node) {
break;
case SystemZISD::USUBO:
NegateOperand = true;
/* fall through */
LLVM_FALLTHROUGH;
case SystemZISD::UADDO:
if (MemVT == MVT::i32)
NewOpc = SystemZ::ALSI;

1
lib/Target/WebAssembly/WebAssemblyFastISel.cpp
View File

@ -447,6 +447,7 @@ unsigned WebAssemblyFastISel::zeroExtendToI32(unsigned Reg, const Value *V,
(isa<Argument>(V) && cast<Argument>(V)->hasZExtAttr()))
return copyValue(Reg);
}
break;
case MVT::i8:
case MVT::i16:
break;

2
lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
View File

@ -1393,7 +1393,7 @@ static int readModRM(struct InternalInstruction* insn) {
break;
case 0x1:
insn->displacementSize = 1;
/* FALLTHROUGH */
LLVM_FALLTHROUGH;
case 0x2:
insn->eaDisplacement = (mod == 0x1 ? EA_DISP_8 : EA_DISP_32);
switch (rm & 7) {