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Recommit "[APInt] Add back the asserts that check that the APInt shift methods aren't called with values larger than BitWidth."

This includes a fix to clamp a right shift of larger than BitWidth in DAG combining.

llvm-svn: 300816
This commit is contained in:
Craig Topper 2017-04-20 03:49:18 +00:00
parent a967cb83eb
commit e49ed4ba3f
3 changed files with 9 additions and 6 deletions

View File

@ -847,8 +847,9 @@ public:
///
/// \returns *this after shifting left by ShiftAmt
APInt &operator<<=(unsigned ShiftAmt) {
assert(ShiftAmt <= BitWidth && "Invalid shift amount");
if (isSingleWord()) {
if (ShiftAmt >= BitWidth)
if (ShiftAmt == BitWidth)
VAL = 0;
else
VAL <<= ShiftAmt;
@ -893,8 +894,9 @@ public:
/// Logical right-shift this APInt by ShiftAmt in place.
void lshrInPlace(unsigned ShiftAmt) {
assert(ShiftAmt <= BitWidth && "Invalid shift amount");
if (isSingleWord()) {
if (ShiftAmt >= BitWidth)
if (ShiftAmt == BitWidth)
VAL = 0;
else
VAL >>= ShiftAmt;

View File

@ -861,11 +861,12 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
InnerOp.getOpcode() == ISD::SRL &&
InnerOp.hasOneUse() &&
isa<ConstantSDNode>(InnerOp.getOperand(1))) {
uint64_t InnerShAmt = cast<ConstantSDNode>(InnerOp.getOperand(1))
unsigned InnerShAmt = cast<ConstantSDNode>(InnerOp.getOperand(1))
->getZExtValue();
if (InnerShAmt < ShAmt &&
InnerShAmt < InnerBits &&
NewMask.lshr(InnerBits - InnerShAmt + ShAmt) == 0 &&
NewMask.lshr(std::min(InnerBits - InnerShAmt + ShAmt,
BitWidth)) == 0 &&
NewMask.trunc(ShAmt) == 0) {
SDValue NewSA =
TLO.DAG.getConstant(ShAmt - InnerShAmt, dl,

View File

@ -2021,7 +2021,7 @@ TEST(APIntTest, LogicalRightShift) {
// Ensure we handle large shifts of multi-word.
const APInt neg_one(128, static_cast<uint64_t>(-1), true);
EXPECT_EQ(0, neg_one.lshr(257));
EXPECT_EQ(0, neg_one.lshr(128));
}
TEST(APIntTest, LeftShift) {
@ -2054,7 +2054,7 @@ TEST(APIntTest, LeftShift) {
// Ensure we handle large shifts of multi-word.
const APInt neg_one(128, static_cast<uint64_t>(-1), true);
EXPECT_EQ(0, neg_one.shl(257));
EXPECT_EQ(0, neg_one.shl(128));
}
} // end anonymous namespace