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Grab the subtarget and subtarget dependent variables off of
MachineFunction rather than TargetMachine. llvm-svn: 219671
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db23ede8d2
commit
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@ -33,7 +33,6 @@
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#include <algorithm>
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using namespace llvm;
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@ -54,7 +53,6 @@ namespace {
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RAFast() : MachineFunctionPass(ID), StackSlotForVirtReg(-1),
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isBulkSpilling(false) {}
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private:
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const TargetMachine *TM;
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MachineFunction *MF;
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MachineRegisterInfo *MRI;
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const TargetRegisterInfo *TRI;
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@ -1078,9 +1076,8 @@ bool RAFast::runOnMachineFunction(MachineFunction &Fn) {
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<< "********** Function: " << Fn.getName() << '\n');
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MF = &Fn;
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MRI = &MF->getRegInfo();
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TM = &Fn.getTarget();
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TRI = TM->getSubtargetImpl()->getRegisterInfo();
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TII = TM->getSubtargetImpl()->getInstrInfo();
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TRI = MF->getSubtarget().getRegisterInfo();
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TII = MF->getSubtarget().getInstrInfo();
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MRI->freezeReservedRegs(Fn);
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RegClassInfo.runOnMachineFunction(Fn);
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UsedInInstr.clear();
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@ -2317,13 +2317,13 @@ bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
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<< "********** Function: " << mf.getName() << '\n');
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MF = &mf;
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const TargetMachine &TM = MF->getTarget();
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TRI = TM.getSubtargetImpl()->getRegisterInfo();
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TII = TM.getSubtargetImpl()->getInstrInfo();
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TRI = MF->getSubtarget().getRegisterInfo();
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TII = MF->getSubtarget().getInstrInfo();
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RCI.runOnMachineFunction(mf);
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EnableLocalReassign = EnableLocalReassignment ||
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TM.getSubtargetImpl()->enableRALocalReassignment(TM.getOptLevel());
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MF->getSubtarget().enableRALocalReassignment(
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MF->getTarget().getOptLevel());
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if (VerifyEnabled)
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MF->verify(this, "Before greedy register allocator");
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@ -24,7 +24,6 @@
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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using namespace llvm;
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@ -63,9 +62,8 @@ void RegScavenger::initRegState() {
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void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
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MachineFunction &MF = *mbb->getParent();
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const TargetMachine &TM = MF.getTarget();
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TII = TM.getSubtargetImpl()->getInstrInfo();
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TRI = TM.getSubtargetImpl()->getRegisterInfo();
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TII = MF.getSubtarget().getInstrInfo();
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TRI = MF.getSubtarget().getRegisterInfo();
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MRI = &MF.getRegInfo();
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assert((NumRegUnits == 0 || NumRegUnits == TRI->getNumRegUnits()) &&
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@ -320,14 +320,8 @@ SplitEditor::SplitEditor(SplitAnalysis &sa, LiveIntervals &lis, VirtRegMap &vrm,
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MachineDominatorTree &mdt,
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MachineBlockFrequencyInfo &mbfi)
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: SA(sa), LIS(lis), VRM(vrm), MRI(vrm.getMachineFunction().getRegInfo()),
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MDT(mdt), TII(*vrm.getMachineFunction()
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.getTarget()
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.getSubtargetImpl()
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->getInstrInfo()),
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TRI(*vrm.getMachineFunction()
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.getTarget()
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.getSubtargetImpl()
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->getRegisterInfo()),
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MDT(mdt), TII(*vrm.getMachineFunction().getSubtarget().getInstrInfo()),
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TRI(*vrm.getMachineFunction().getSubtarget().getRegisterInfo()),
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MBFI(mbfi), Edit(nullptr), OpenIdx(0), SpillMode(SM_Partition),
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RegAssign(Allocator) {}
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