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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 11:13:28 +01:00

Grab the subtarget and subtarget dependent variables off of

MachineFunction rather than TargetMachine.

llvm-svn: 219671
This commit is contained in:
Eric Christopher 2014-10-14 07:22:00 +00:00
parent db23ede8d2
commit e4d58538b3
4 changed files with 10 additions and 21 deletions

View File

@ -33,7 +33,6 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
using namespace llvm;
@ -54,7 +53,6 @@ namespace {
RAFast() : MachineFunctionPass(ID), StackSlotForVirtReg(-1),
isBulkSpilling(false) {}
private:
const TargetMachine *TM;
MachineFunction *MF;
MachineRegisterInfo *MRI;
const TargetRegisterInfo *TRI;
@ -1078,9 +1076,8 @@ bool RAFast::runOnMachineFunction(MachineFunction &Fn) {
<< "********** Function: " << Fn.getName() << '\n');
MF = &Fn;
MRI = &MF->getRegInfo();
TM = &Fn.getTarget();
TRI = TM->getSubtargetImpl()->getRegisterInfo();
TII = TM->getSubtargetImpl()->getInstrInfo();
TRI = MF->getSubtarget().getRegisterInfo();
TII = MF->getSubtarget().getInstrInfo();
MRI->freezeReservedRegs(Fn);
RegClassInfo.runOnMachineFunction(Fn);
UsedInInstr.clear();

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@ -2317,13 +2317,13 @@ bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
<< "********** Function: " << mf.getName() << '\n');
MF = &mf;
const TargetMachine &TM = MF->getTarget();
TRI = TM.getSubtargetImpl()->getRegisterInfo();
TII = TM.getSubtargetImpl()->getInstrInfo();
TRI = MF->getSubtarget().getRegisterInfo();
TII = MF->getSubtarget().getInstrInfo();
RCI.runOnMachineFunction(mf);
EnableLocalReassign = EnableLocalReassignment ||
TM.getSubtargetImpl()->enableRALocalReassignment(TM.getOptLevel());
MF->getSubtarget().enableRALocalReassignment(
MF->getTarget().getOptLevel());
if (VerifyEnabled)
MF->verify(this, "Before greedy register allocator");

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@ -24,7 +24,6 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
@ -63,9 +62,8 @@ void RegScavenger::initRegState() {
void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
MachineFunction &MF = *mbb->getParent();
const TargetMachine &TM = MF.getTarget();
TII = TM.getSubtargetImpl()->getInstrInfo();
TRI = TM.getSubtargetImpl()->getRegisterInfo();
TII = MF.getSubtarget().getInstrInfo();
TRI = MF.getSubtarget().getRegisterInfo();
MRI = &MF.getRegInfo();
assert((NumRegUnits == 0 || NumRegUnits == TRI->getNumRegUnits()) &&

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@ -320,14 +320,8 @@ SplitEditor::SplitEditor(SplitAnalysis &sa, LiveIntervals &lis, VirtRegMap &vrm,
MachineDominatorTree &mdt,
MachineBlockFrequencyInfo &mbfi)
: SA(sa), LIS(lis), VRM(vrm), MRI(vrm.getMachineFunction().getRegInfo()),
MDT(mdt), TII(*vrm.getMachineFunction()
.getTarget()
.getSubtargetImpl()
->getInstrInfo()),
TRI(*vrm.getMachineFunction()
.getTarget()
.getSubtargetImpl()
->getRegisterInfo()),
MDT(mdt), TII(*vrm.getMachineFunction().getSubtarget().getInstrInfo()),
TRI(*vrm.getMachineFunction().getSubtarget().getRegisterInfo()),
MBFI(mbfi), Edit(nullptr), OpenIdx(0), SpillMode(SM_Partition),
RegAssign(Allocator) {}