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Grab the subtarget and subtarget dependent variables off of

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MachineFunction rather than TargetMachine.

llvm-svn: 219671
This commit is contained in:
Eric Christopher 2014-10-14 07:22:00 +00:00
parent db23ede8d2
commit e4d58538b3
4 changed files with 10 additions and 21 deletions
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7
lib/CodeGen/RegAllocFast.cpp
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@ -33,7 +33,6 @@
#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h" #include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetSubtargetInfo.h" #include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm> #include <algorithm>
using namespace llvm; using namespace llvm;
@ -54,7 +53,6 @@ namespace {
RAFast() : MachineFunctionPass(ID), StackSlotForVirtReg(-1), RAFast() : MachineFunctionPass(ID), StackSlotForVirtReg(-1),
isBulkSpilling(false) {} isBulkSpilling(false) {}
private: private:
const TargetMachine *TM;
MachineFunction *MF; MachineFunction *MF;
MachineRegisterInfo *MRI; MachineRegisterInfo *MRI;
const TargetRegisterInfo *TRI; const TargetRegisterInfo *TRI;
@ -1078,9 +1076,8 @@ bool RAFast::runOnMachineFunction(MachineFunction &Fn) {
<< "********** Function: " << Fn.getName() << '\n'); << "********** Function: " << Fn.getName() << '\n');
MF = &Fn; MF = &Fn;
MRI = &MF->getRegInfo(); MRI = &MF->getRegInfo();
TM = &Fn.getTarget(); TRI = MF->getSubtarget().getRegisterInfo();
TRI = TM->getSubtargetImpl()->getRegisterInfo(); TII = MF->getSubtarget().getInstrInfo();
TII = TM->getSubtargetImpl()->getInstrInfo();
MRI->freezeReservedRegs(Fn); MRI->freezeReservedRegs(Fn);
RegClassInfo.runOnMachineFunction(Fn); RegClassInfo.runOnMachineFunction(Fn);
UsedInInstr.clear(); UsedInInstr.clear();

8
lib/CodeGen/RegAllocGreedy.cpp
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@ -2317,13 +2317,13 @@ bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
<< "********** Function: " << mf.getName() << '\n'); << "********** Function: " << mf.getName() << '\n');
MF = &mf; MF = &mf;
const TargetMachine &TM = MF->getTarget(); TRI = MF->getSubtarget().getRegisterInfo();
TRI = TM.getSubtargetImpl()->getRegisterInfo(); TII = MF->getSubtarget().getInstrInfo();
TII = TM.getSubtargetImpl()->getInstrInfo();
RCI.runOnMachineFunction(mf); RCI.runOnMachineFunction(mf);
EnableLocalReassign = EnableLocalReassignment || EnableLocalReassign = EnableLocalReassignment ||
TM.getSubtargetImpl()->enableRALocalReassignment(TM.getOptLevel()); MF->getSubtarget().enableRALocalReassignment(
MF->getTarget().getOptLevel());
if (VerifyEnabled) if (VerifyEnabled)
MF->verify(this, "Before greedy register allocator"); MF->verify(this, "Before greedy register allocator");

6
lib/CodeGen/RegisterScavenging.cpp
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@ -24,7 +24,6 @@
#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h" #include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h" #include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm; using namespace llvm;
@ -63,9 +62,8 @@ void RegScavenger::initRegState() {
void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) { void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
MachineFunction &MF = *mbb->getParent(); MachineFunction &MF = *mbb->getParent();
const TargetMachine &TM = MF.getTarget(); TII = MF.getSubtarget().getInstrInfo();
TII = TM.getSubtargetImpl()->getInstrInfo(); TRI = MF.getSubtarget().getRegisterInfo();
TRI = TM.getSubtargetImpl()->getRegisterInfo();
MRI = &MF.getRegInfo(); MRI = &MF.getRegInfo();
assert((NumRegUnits == 0 || NumRegUnits == TRI->getNumRegUnits()) && assert((NumRegUnits == 0 || NumRegUnits == TRI->getNumRegUnits()) &&

10
lib/CodeGen/SplitKit.cpp
View File

@ -320,14 +320,8 @@ SplitEditor::SplitEditor(SplitAnalysis &sa, LiveIntervals &lis, VirtRegMap &vrm,
MachineDominatorTree &mdt, MachineDominatorTree &mdt,
MachineBlockFrequencyInfo &mbfi) MachineBlockFrequencyInfo &mbfi)
: SA(sa), LIS(lis), VRM(vrm), MRI(vrm.getMachineFunction().getRegInfo()), : SA(sa), LIS(lis), VRM(vrm), MRI(vrm.getMachineFunction().getRegInfo()),
MDT(mdt), TII(*vrm.getMachineFunction() MDT(mdt), TII(*vrm.getMachineFunction().getSubtarget().getInstrInfo()),
.getTarget() TRI(*vrm.getMachineFunction().getSubtarget().getRegisterInfo()),
.getSubtargetImpl()
->getInstrInfo()),
TRI(*vrm.getMachineFunction()
.getTarget()
.getSubtargetImpl()
->getRegisterInfo()),
MBFI(mbfi), Edit(nullptr), OpenIdx(0), SpillMode(SM_Partition), MBFI(mbfi), Edit(nullptr), OpenIdx(0), SpillMode(SM_Partition),
RegAssign(Allocator) {} RegAssign(Allocator) {}