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[AArch64] Fix comparison peephole opt with non-0/1 immediate (PR51476)
This is a non-intrusive fix for https://bugs.llvm.org/show_bug.cgi?id=51476 intended for backport to the 13.x release branch. It expands on the current hack by distinguishing between CmpValue of 0, 1 and 2, where 0 and 1 have the obvious meaning and 2 means "anything else". The new optimization from D98564 should only be performed for CmpValue of 0 or 1. For main, I think we should switch the analyzeCompare() and optimizeCompare() APIs to use int64_t instead of int, which is in line with MachineOperand's notion of an immediate, and avoids this problem altogether. Differential Revision: https://reviews.llvm.org/D108076 (cherry picked from commit 81b106584f2baf33e09be2362c35c1bf2f6bfe94)
This commit is contained in:
Nikita Popov
Tom Stellard
parent
45d26b8826
commit
e4e6f3eeff
@ -1120,6 +1120,16 @@ bool AArch64InstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,
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if (!MI.getOperand(1).isReg())
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return false;
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auto NormalizeCmpValue = [](int64_t Value) -> int {
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// Comparison immediates may be 64-bit, but CmpValue is only an int.
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// Normalize to 0/1/2 return value, where 2 indicates any value apart from
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// 0 or 1.
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// TODO: Switch CmpValue to int64_t in the API to avoid this.
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if (Value == 0 || Value == 1)
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return Value;
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return 2;
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};
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switch (MI.getOpcode()) {
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default:
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break;
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@ -1155,8 +1165,7 @@ bool AArch64InstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,
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SrcReg = MI.getOperand(1).getReg();
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SrcReg2 = 0;
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CmpMask = ~0;
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// FIXME: In order to convert CmpValue to 0 or 1
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CmpValue = MI.getOperand(2).getImm() != 0;
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CmpValue = NormalizeCmpValue(MI.getOperand(2).getImm());
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return true;
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case AArch64::ANDSWri:
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case AArch64::ANDSXri:
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@ -1165,14 +1174,9 @@ bool AArch64InstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,
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SrcReg = MI.getOperand(1).getReg();
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SrcReg2 = 0;
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CmpMask = ~0;
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// FIXME:The return val type of decodeLogicalImmediate is uint64_t,
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// while the type of CmpValue is int. When converting uint64_t to int,
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// the high 32 bits of uint64_t will be lost.
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// In fact it causes a bug in spec2006-483.xalancbmk
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// CmpValue is only used to compare with zero in OptimizeCompareInstr
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CmpValue = AArch64_AM::decodeLogicalImmediate(
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CmpValue = NormalizeCmpValue(AArch64_AM::decodeLogicalImmediate(
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MI.getOperand(2).getImm(),
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MI.getOpcode() == AArch64::ANDSWri ? 32 : 64) != 0;
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MI.getOpcode() == AArch64::ANDSWri ? 32 : 64));
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return true;
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}
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@ -1462,10 +1466,9 @@ bool AArch64InstrInfo::optimizeCompareInstr(
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if (CmpInstr.getOpcode() == AArch64::PTEST_PP)
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return optimizePTestInstr(&CmpInstr, SrcReg, SrcReg2, MRI);
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// Continue only if we have a "ri" where immediate is zero.
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// FIXME:CmpValue has already been converted to 0 or 1 in analyzeCompare
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// function.
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assert((CmpValue == 0 || CmpValue == 1) && "CmpValue must be 0 or 1!");
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// Warning: CmpValue == 2 indicates *any* value apart from 0 or 1.
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assert((CmpValue == 0 || CmpValue == 1 || CmpValue == 2) &&
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"CmpValue must be 0, 1, or 2!");
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if (SrcReg2 != 0)
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return false;
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@ -1473,9 +1476,10 @@ bool AArch64InstrInfo::optimizeCompareInstr(
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if (!MRI->use_nodbg_empty(CmpInstr.getOperand(0).getReg()))
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return false;
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if (!CmpValue && substituteCmpToZero(CmpInstr, SrcReg, *MRI))
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if (CmpValue == 0 && substituteCmpToZero(CmpInstr, SrcReg, *MRI))
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return true;
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return removeCmpToZeroOrOne(CmpInstr, SrcReg, CmpValue, *MRI);
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return (CmpValue == 0 || CmpValue == 1) &&
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removeCmpToZeroOrOne(CmpInstr, SrcReg, CmpValue, *MRI);
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}
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/// Get opcode of S version of Instr.
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@ -307,3 +307,42 @@ body: |
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RET_ReallyLR
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...
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---
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name: subswr_wrong_cmp_value
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: subswr_wrong_cmp_value
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; CHECK: bb.0:
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; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK: liveins: $x1
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; CHECK: [[COPY:%[0-9]+]]:gpr64common = COPY $x1
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; CHECK: [[DEF:%[0-9]+]]:gpr64 = IMPLICIT_DEF
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; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr killed [[DEF]], [[COPY]], implicit-def $nzcv
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; CHECK: [[CSINCWr:%[0-9]+]]:gpr32common = CSINCWr $wzr, $wzr, 1, implicit $nzcv
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; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri killed [[CSINCWr]], 3, 0, implicit-def $nzcv
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; CHECK: Bcc 1, %bb.2, implicit $nzcv
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; CHECK: B %bb.1
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; CHECK: bb.1:
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; CHECK: successors: %bb.2(0x80000000)
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; CHECK: B %bb.2
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; CHECK: bb.2:
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; CHECK: RET_ReallyLR
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bb.0:
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liveins: $x1
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successors: %bb.1(0x40000000), %bb.2(0x40000000)
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%1:gpr64common = COPY $x1
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%2:gpr64 = IMPLICIT_DEF
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%3:gpr64 = SUBSXrr killed %2:gpr64, %1:gpr64common, implicit-def $nzcv
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%4:gpr32common = CSINCWr $wzr, $wzr, 1, implicit $nzcv
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%5:gpr32 = SUBSWri killed %4:gpr32common, 3, 0, implicit-def $nzcv
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Bcc 1, %bb.2, implicit $nzcv
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B %bb.1
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bb.1:
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successors: %bb.2(0x80000000)
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B %bb.2
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bb.2:
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RET_ReallyLR
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...
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35
test/CodeGen/AArch64/pr51476.ll
Normal file
35
test/CodeGen/AArch64/pr51476.ll
Normal file
@ -0,0 +1,35 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
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define void @test(i8 %arg) nounwind {
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; CHECK-LABEL: test:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: and w8, w0, #0xff
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; CHECK-NEXT: cmp w8, #1
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; CHECK-NEXT: cset w0, ne
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; CHECK-NEXT: cmp w0, #3
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; CHECK-NEXT: strb w0, [sp, #12]
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; CHECK-NEXT: b.eq .LBB0_2
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; CHECK-NEXT: // %bb.1: // %do_call
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; CHECK-NEXT: bl unknown
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; CHECK-NEXT: .LBB0_2: // %common.ret
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; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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%tmp = alloca i8
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%cmp1 = icmp ne i8 %arg, 1
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%zext = zext i1 %cmp1 to i8
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store i8 %zext, i8* %tmp
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%zext2 = load i8, i8* %tmp
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%cmp2 = icmp eq i8 %zext2, 3
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br i1 %cmp2, label %exit, label %do_call
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do_call:
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call void @unknown(i8 %zext2)
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ret void
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exit:
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ret void
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}
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declare void @unknown(i8)
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