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[ARM] Optimise ASRL/LSRL to smaller shifts using demand bits.
The ASRL/LSRL long shifts are generated from 64bit shifts. Once we have them, it might turn out that enough of the 64bit result was not required that we can use a smaller shift to perform the same result. As the smaller shift can in general be folded in more way, such as into add instructions in one of the test cases here, we can use the demand bit analysis to prefer the smaller shifts where we can. Differential Revision: https://reviews.llvm.org/D75371
This commit is contained in:
David Green
parent
4d56b10105
commit
e547a3cc78
@ -16229,6 +16229,35 @@ ARMTargetLowering::targetShrinkDemandedConstant(SDValue Op,
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return false;
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}
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bool ARMTargetLowering::SimplifyDemandedBitsForTargetNode(
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SDValue Op, const APInt &OriginalDemandedBits,
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const APInt &OriginalDemandedElts, KnownBits &Known, TargetLoweringOpt &TLO,
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unsigned Depth) const {
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unsigned Opc = Op.getOpcode();
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switch (Opc) {
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case ARMISD::ASRL:
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case ARMISD::LSRL: {
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// If this is result 0 and the other result is unused, see if the demand
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// bits allow us to shrink this long shift into a standard small shift in
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// the opposite direction.
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if (Op.getResNo() == 0 && !Op->hasAnyUseOfValue(1) &&
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isa<ConstantSDNode>(Op->getOperand(2))) {
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unsigned ShAmt = Op->getConstantOperandVal(2);
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if (ShAmt < 32 && OriginalDemandedBits.isSubsetOf(
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APInt::getAllOnesValue(32) << (32 - ShAmt)))
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return TLO.CombineTo(
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Op, TLO.DAG.getNode(
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ISD::SHL, SDLoc(Op), MVT::i32, Op.getOperand(1),
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TLO.DAG.getConstant(32 - ShAmt, SDLoc(Op), MVT::i32)));
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}
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break;
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}
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}
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return TargetLowering::SimplifyDemandedBitsForTargetNode(
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Op, OriginalDemandedBits, OriginalDemandedElts, Known, TLO, Depth);
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}
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//===----------------------------------------------------------------------===//
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// ARM Inline Assembly Support
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@ -354,6 +354,13 @@ class VectorType;
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SDValue PerformCMOVToBFICombine(SDNode *N, SelectionDAG &DAG) const;
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SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
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bool SimplifyDemandedBitsForTargetNode(SDValue Op,
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const APInt &OriginalDemandedBits,
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const APInt &OriginalDemandedElts,
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KnownBits &Known,
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TargetLoweringOpt &TLO,
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unsigned Depth) const override;
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bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override;
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/// allowsMisalignedMemoryAccesses - Returns true if the target allows
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@ -3,27 +3,15 @@
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; RUN: llc --verify-machineinstrs -mtriple=thumbv8.1m.main-none-eabi -mattr=+dsp %s -o - | FileCheck %s -check-prefix=CHECK --check-prefix=CHECK-NOMVE
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define void @test1(i32* %p0, i32 *%p1, i32 *%p2, i32 *%pDst) {
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; CHECK-MVE-LABEL: test1:
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; CHECK-MVE: @ %bb.0: @ %entry
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; CHECK-MVE-NEXT: ldr r1, [r1]
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; CHECK-MVE-NEXT: ldr r2, [r2]
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; CHECK-MVE-NEXT: ldr r0, [r0]
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; CHECK-MVE-NEXT: smull r2, r1, r2, r1
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; CHECK-MVE-NEXT: lsrl r2, r1, #31
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; CHECK-MVE-NEXT: bic r1, r2, #1
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; CHECK-MVE-NEXT: add r0, r1
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; CHECK-MVE-NEXT: str r0, [r3]
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; CHECK-MVE-NEXT: bx lr
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;
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; CHECK-NOMVE-LABEL: test1:
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; CHECK-NOMVE: @ %bb.0: @ %entry
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; CHECK-NOMVE-NEXT: ldr r1, [r1]
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; CHECK-NOMVE-NEXT: ldr r2, [r2]
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; CHECK-NOMVE-NEXT: ldr r0, [r0]
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; CHECK-NOMVE-NEXT: smmul r1, r2, r1
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; CHECK-NOMVE-NEXT: add.w r0, r0, r1, lsl #1
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; CHECK-NOMVE-NEXT: str r0, [r3]
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; CHECK-NOMVE-NEXT: bx lr
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; CHECK-LABEL: test1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: ldr r1, [r1]
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; CHECK-NEXT: ldr r2, [r2]
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; CHECK-NEXT: ldr r0, [r0]
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; CHECK-NEXT: smmul r1, r2, r1
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; CHECK-NEXT: add.w r0, r0, r1, lsl #1
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; CHECK-NEXT: str r0, [r3]
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; CHECK-NEXT: bx lr
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entry:
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%l3 = load i32, i32* %p0, align 4
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%l4 = load i32, i32* %p1, align 4
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@ -422,16 +422,10 @@ entry:
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define i32 @ashr_demand_bottommask(i64 %x) {
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; CHECK-MVE-LABEL: ashr_demand_bottommask:
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; CHECK-MVE: @ %bb.0: @ %entry
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; CHECK-MVE-NEXT: lsrl r0, r1, #31
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; CHECK-MVE-NEXT: bic r0, r0, #1
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; CHECK-MVE-NEXT: bx lr
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;
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; CHECK-NON-MVE-LABEL: ashr_demand_bottommask:
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; CHECK-NON-MVE: @ %bb.0: @ %entry
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; CHECK-NON-MVE-NEXT: lsls r0, r1, #1
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; CHECK-NON-MVE-NEXT: bx lr
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; CHECK-LABEL: ashr_demand_bottommask:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: lsls r0, r1, #1
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; CHECK-NEXT: bx lr
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entry:
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%shr = ashr i64 %x, 31
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%t = trunc i64 %shr to i32
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@ -440,16 +434,10 @@ entry:
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}
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define i32 @lshr_demand_bottommask(i64 %x) {
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; CHECK-MVE-LABEL: lshr_demand_bottommask:
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; CHECK-MVE: @ %bb.0: @ %entry
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; CHECK-MVE-NEXT: lsrl r0, r1, #31
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; CHECK-MVE-NEXT: bic r0, r0, #1
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; CHECK-MVE-NEXT: bx lr
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;
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; CHECK-NON-MVE-LABEL: lshr_demand_bottommask:
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; CHECK-NON-MVE: @ %bb.0: @ %entry
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; CHECK-NON-MVE-NEXT: lsls r0, r1, #1
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; CHECK-NON-MVE-NEXT: bx lr
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; CHECK-LABEL: lshr_demand_bottommask:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: lsls r0, r1, #1
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; CHECK-NEXT: bx lr
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entry:
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%shr = lshr i64 %x, 31
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%t = trunc i64 %shr to i32
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@ -470,17 +458,11 @@ entry:
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}
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define i32 @ashr_demand_bottommask2(i64 %x) {
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; CHECK-MVE-LABEL: ashr_demand_bottommask2:
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; CHECK-MVE: @ %bb.0: @ %entry
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; CHECK-MVE-NEXT: lsrl r0, r1, #31
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; CHECK-MVE-NEXT: bic r0, r0, #3
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; CHECK-MVE-NEXT: bx lr
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;
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; CHECK-NON-MVE-LABEL: ashr_demand_bottommask2:
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; CHECK-NON-MVE: @ %bb.0: @ %entry
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; CHECK-NON-MVE-NEXT: mvn r0, #2
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; CHECK-NON-MVE-NEXT: and.w r0, r0, r1, lsl #1
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; CHECK-NON-MVE-NEXT: bx lr
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; CHECK-LABEL: ashr_demand_bottommask2:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: mvn r0, #2
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; CHECK-NEXT: and.w r0, r0, r1, lsl #1
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; CHECK-NEXT: bx lr
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entry:
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%shr = ashr i64 %x, 31
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%t = trunc i64 %shr to i32
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@ -489,17 +471,11 @@ entry:
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}
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define i32 @lshr_demand_bottommask2(i64 %x) {
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; CHECK-MVE-LABEL: lshr_demand_bottommask2:
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; CHECK-MVE: @ %bb.0: @ %entry
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; CHECK-MVE-NEXT: lsrl r0, r1, #31
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; CHECK-MVE-NEXT: bic r0, r0, #3
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; CHECK-MVE-NEXT: bx lr
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;
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; CHECK-NON-MVE-LABEL: lshr_demand_bottommask2:
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; CHECK-NON-MVE: @ %bb.0: @ %entry
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; CHECK-NON-MVE-NEXT: mvn r0, #2
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; CHECK-NON-MVE-NEXT: and.w r0, r0, r1, lsl #1
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; CHECK-NON-MVE-NEXT: bx lr
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; CHECK-LABEL: lshr_demand_bottommask2:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: mvn r0, #2
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; CHECK-NEXT: and.w r0, r0, r1, lsl #1
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; CHECK-NEXT: bx lr
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entry:
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%shr = lshr i64 %x, 31
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%t = trunc i64 %shr to i32
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