RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 03:02:36 +01:00
Code Issues Projects Releases Wiki Activity

Add patterns for matching immediates whose lower 16-bit is cleared. These

Browse Source 
patterns emit a single LUi instruction instead of a pair of LUi and ORi.

llvm-svn: 146900
This commit is contained in:
Akira Hatanaka 2011-12-19 20:21:18 +00:00
parent 602ab7a677
commit e54da3bfa2
4 changed files with 21 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
lib/Target/Mips/Mips64InstrInfo.td
View File

@ -225,6 +225,8 @@ def : Pat<(i64 immSExt16:$in),
(DADDiu ZERO_64, imm:$in)>;
def : Pat<(i64 immZExt16:$in),
(ORi64 ZERO_64, imm:$in)>;
def : Pat<(i64 immLUiOpnd:$in),
(LUi64 (HI16 imm:$in))>;
// 32-bit immediates
def : Pat<(i64 immSExt32:$imm),

8
lib/Target/Mips/MipsInstrInfo.td
View File

@ -219,6 +219,12 @@ def immZExt16 : PatLeaf<(imm), [{
return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
}], LO16>;
// Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
def immLUiOpnd : PatLeaf<(imm), [{
int64_t Val = N->getSExtValue();
return isInt<32>(Val) && !(Val & 0xffff);
}]>;
// shamt field must fit in 5 bits.
def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
@ -933,6 +939,8 @@ def : Pat<(i32 immSExt16:$in),
(ADDiu ZERO, imm:$in)>;
def : Pat<(i32 immZExt16:$in),
(ORi ZERO, imm:$in)>;
def : Pat<(i32 immLUiOpnd:$in),
(LUi (HI16 imm:$in))>;
// Arbitrary immediates
def : Pat<(i32 imm:$imm),

9
test/CodeGen/Mips/fcopysign.ll
View File

@ -5,9 +5,8 @@
define double @func0(double %d0, double %d1) nounwind readnone {
entry:
; MIPS32-EL: func0:
; MIPS32-EL: lui $[[T1:[0-9]+]], 32768
; MIPS32-EL: ori $[[MSK1:[0-9]+]], $[[T1]], 0
; MIPS32-EL: mfc1 $[[HI0:[0-9]+]], $f15
; MIPS32-EL: lui $[[MSK1:[0-9]+]], 32768
; MIPS32-EL: and $[[AND1:[0-9]+]], $[[HI0]], $[[MSK1]]
; MIPS32-EL: lui $[[T0:[0-9]+]], 32767
; MIPS32-EL: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
@ -18,9 +17,8 @@ entry:
; MIPS32-EL: mtc1 $[[LO0]], $f0
; MIPS32-EL: mtc1 $[[OR]], $f1
;
; MIPS32-EB: lui $[[T1:[0-9]+]], 32768
; MIPS32-EB: ori $[[MSK1:[0-9]+]], $[[T1]], 0
; MIPS32-EB: mfc1 $[[HI1:[0-9]+]], $f14
; MIPS32-EB: lui $[[MSK1:[0-9]+]], 32768
; MIPS32-EB: and $[[AND1:[0-9]+]], $[[HI1]], $[[MSK1]]
; MIPS32-EB: lui $[[T0:[0-9]+]], 32767
; MIPS32-EB: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
@ -46,9 +44,8 @@ declare double @copysign(double, double) nounwind readnone
define float @func1(float %f0, float %f1) nounwind readnone {
entry:
; MIPS32-EL: func1:
; MIPS32-EL: lui $[[T1:[0-9]+]], 32768
; MIPS32-EL: ori $[[MSK1:[0-9]+]], $[[T1]], 0
; MIPS32-EL: mfc1 $[[ARG1:[0-9]+]], $f14
; MIPS32-EL: lui $[[MSK1:[0-9]+]], 32768
; MIPS32-EL: and $[[T3:[0-9]+]], $[[ARG1]], $[[MSK1]]
; MIPS32-EL: lui $[[T0:[0-9]+]], 32767
; MIPS32-EL: ori $[[MSK0:[0-9]+]], $[[T0]], 65535

8
test/CodeGen/Mips/mips64imm.ll
View File

@ -1,5 +1,13 @@
; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s
define i32 @foo1() nounwind readnone {
entry:
; CHECK: foo1
; CHECK: lui ${{[0-9]+}}, 4660
; CHECK-NOT: ori
ret i32 305397760
}
define i64 @foo3() nounwind readnone {
entry:
; CHECK: foo3