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AMDGPU: Start selecting v_mad_mixlo_f16
Also add some tests that should be able to use v_mad_mixhi_f16, but do not yet. This is trickier because we don't really model the partial update of the register done by 16-bit instructions. llvm-svn: 313806
This commit is contained in:
Matt Arsenault
parent
a7c52cebfb
commit
e558077eb1
@ -197,6 +197,7 @@ private:
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bool SelectVOP3OpSelMods0(SDValue In, SDValue &Src, SDValue &SrcMods,
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SDValue &Clamp) const;
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bool SelectVOP3PMadMixModsImpl(SDValue In, SDValue &Src, unsigned &Mods) const;
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bool SelectVOP3PMadMixMods(SDValue In, SDValue &Src, SDValue &SrcMods) const;
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void SelectADD_SUB_I64(SDNode *N);
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void SelectUADDO_USUBO(SDNode *N);
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@ -1990,6 +1991,14 @@ bool AMDGPUDAGToDAGISel::SelectVOP3PMadMixModsImpl(SDValue In, SDValue &Src,
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return false;
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}
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bool AMDGPUDAGToDAGISel::SelectVOP3PMadMixMods(SDValue In, SDValue &Src,
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SDValue &SrcMods) const {
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unsigned Mods = 0;
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SelectVOP3PMadMixModsImpl(In, Src, Mods);
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SrcMods = CurDAG->getTargetConstant(Mods, SDLoc(In), MVT::i32);
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return true;
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}
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void AMDGPUDAGToDAGISel::PostprocessISelDAG() {
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const AMDGPUTargetLowering& Lowering =
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*static_cast<const AMDGPUTargetLowering*>(getTargetLowering());
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@ -68,10 +68,26 @@ def V_PK_LSHRREV_B16 : VOP3PInst<"v_pk_lshrrev_b16", VOP3_Profile<VOP_V2I16_V2I1
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// For 16-bit src arguments their location (hi/lo) are controlled by op_sel_hi.
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let isCommutable = 1 in {
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def V_MAD_MIX_F32 : VOP3_VOP3PInst<"v_mad_mix_f32", VOP3_Profile<VOP_F32_F16_F16_F16, VOP3_OPSEL>>;
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// Clamp modifier is applied after conversion to f16.
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def V_MAD_MIXLO_F16 : VOP3_VOP3PInst<"v_mad_mixlo_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>>;
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def V_MAD_MIXHI_F16 : VOP3_VOP3PInst<"v_mad_mixhi_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>>;
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}
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let Predicates = [HasMadMix] in {
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def : Pat <
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(f16 (fpround (fmad (f32 (VOP3PMadMixMods f16:$src0, i32:$src0_modifiers)),
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(f32 (VOP3PMadMixMods f16:$src1, i32:$src1_modifiers)),
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(f32 (VOP3PMadMixMods f16:$src2, i32:$src2_modifiers))))),
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(V_MAD_MIXLO_F16 $src0_modifiers, $src0,
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$src1_modifiers, $src1,
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$src2_modifiers, $src2,
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0)
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>;
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} // End Predicates = [HasMadMix]
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multiclass VOP3P_Real_vi<bits<10> op> {
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def _vi : VOP3P_Real<!cast<VOP3P_Pseudo>(NAME), SIEncodingFamily.VI>,
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VOP3Pe <op, !cast<VOP3P_Pseudo>(NAME).Pfl> {
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120
test/CodeGen/AMDGPU/mad-mix-hi.ll
Normal file
120
test/CodeGen/AMDGPU/mad-mix-hi.ll
Normal file
@ -0,0 +1,120 @@
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; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
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; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CIVI,VI %s
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; RUN: llc -march=amdgcn -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CIVI,CI %s
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; FIXME: These cases should be able to use v_mad_mixhi_f16 and avoid
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; the packing.
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; GCN-LABEL: {{^}}v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo:
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; GFX9: v_mad_mixlo_f16
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; GFX9: v_lshl_or_b32
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define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo(half %src0, half %src1, half %src2) #0 {
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%src0.ext = fpext half %src0 to float
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%src1.ext = fpext half %src1 to float
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%src2.ext = fpext half %src2 to float
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%result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2.ext)
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%cvt.result = fptrunc float %result to half
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%vec.result = insertelement <2 x half> undef, half %cvt.result, i32 1
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ret <2 x half> %vec.result
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}
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; GCN-LABEL: {{^}}v_mad_mixhi_f16_f16lo_f16lo_f16lo_constlo:
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; GFX9: v_mad_mixlo_f16
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; GFX9: v_lshl_or_b32
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define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_constlo(half %src0, half %src1, half %src2) #0 {
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%src0.ext = fpext half %src0 to float
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%src1.ext = fpext half %src1 to float
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%src2.ext = fpext half %src2 to float
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%result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2.ext)
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%cvt.result = fptrunc float %result to half
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%vec.result = insertelement <2 x half> <half 1.0, half undef>, half %cvt.result, i32 1
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ret <2 x half> %vec.result
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}
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; GCN-LABEL: {{^}}v_mad_mixhi_f16_f16lo_f16lo_f16lo_reglo:
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; GFX9: v_mad_mixlo_f16
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; GFX9: v_lshl_or_b32
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define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_reglo(half %src0, half %src1, half %src2, half %lo) #0 {
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%src0.ext = fpext half %src0 to float
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%src1.ext = fpext half %src1 to float
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%src2.ext = fpext half %src2 to float
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%result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2.ext)
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%cvt.result = fptrunc float %result to half
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%vec = insertelement <2 x half> undef, half %lo, i32 0
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%vec.result = insertelement <2 x half> %vec, half %cvt.result, i32 1
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ret <2 x half> %vec.result
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}
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; GCN-LABEL: {{^}}v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack:
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; GFX9: v_mad_mixlo_f16 v0, v0, v1, v2
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; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
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define i32 @v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack(half %src0, half %src1, half %src2) #0 {
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%src0.ext = fpext half %src0 to float
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%src1.ext = fpext half %src1 to float
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%src2.ext = fpext half %src2 to float
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%result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2.ext)
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%cvt.result = fptrunc float %result to half
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%bc = bitcast half %cvt.result to i16
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%ext = zext i16 %bc to i32
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%shr = shl i32 %ext, 16
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ret i32 %shr
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}
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; GCN-LABEL: {{^}}v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack_sext:
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; GFX9: v_mad_mixlo_f16 v0, v0, v1, v2
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; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
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define i32 @v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack_sext(half %src0, half %src1, half %src2) #0 {
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%src0.ext = fpext half %src0 to float
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%src1.ext = fpext half %src1 to float
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%src2.ext = fpext half %src2 to float
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%result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2.ext)
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%cvt.result = fptrunc float %result to half
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%bc = bitcast half %cvt.result to i16
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%ext = sext i16 %bc to i32
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%shr = shl i32 %ext, 16
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ret i32 %shr
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}
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; GCN-LABEL: {{^}}v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt:
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; GFX9: v_mad_mix_f32 v0, v0, v1, v2 clamp{{$}}
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; GFX9: v_cvt_f16_f32_e32 v0, v0
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define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt(half %src0, half %src1, half %src2) #0 {
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%src0.ext = fpext half %src0 to float
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%src1.ext = fpext half %src1 to float
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%src2.ext = fpext half %src2 to float
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%result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2.ext)
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%max = call float @llvm.maxnum.f32(float %result, float 0.0)
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%clamp = call float @llvm.minnum.f32(float %max, float 1.0)
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%cvt.result = fptrunc float %clamp to half
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%vec.result = insertelement <2 x half> undef, half %cvt.result, i32 1
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ret <2 x half> %vec.result
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}
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; FIXME: Unnecessary junk to pack, and packing undef?
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; GCN-LABEL: {{^}}v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_postcvt:
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; GFX9: v_mad_mixlo_f16 v0, v0, v1, v2 clamp{{$}}
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; GFX9-NEXT: v_mov_b32_e32 [[MASK:v[0-9]+]], 0xffff{{$}}
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; GFX9-NEXT: v_and_b32_e32 [[AND:v[0-9]+]], s6, [[MASK]]
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; GFX9-NEXT: v_lshl_or_b32 v0, v0, 16, [[AND]]
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; GFX9-NEXT: s_setpc_b64
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define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_postcvt(half %src0, half %src1, half %src2) #0 {
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%src0.ext = fpext half %src0 to float
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%src1.ext = fpext half %src1 to float
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%src2.ext = fpext half %src2 to float
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%result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2.ext)
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%cvt.result = fptrunc float %result to half
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%max = call half @llvm.maxnum.f16(half %cvt.result, half 0.0)
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%clamp = call half @llvm.minnum.f16(half %max, half 1.0)
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%vec.result = insertelement <2 x half> undef, half %clamp, i32 1
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ret <2 x half> %vec.result
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}
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declare half @llvm.minnum.f16(half, half) #1
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declare half @llvm.maxnum.f16(half, half) #1
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declare float @llvm.minnum.f32(float, float) #1
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declare float @llvm.maxnum.f32(float, float) #1
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declare float @llvm.fmuladd.f32(float, float, float) #1
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declare <2 x float> @llvm.fmuladd.v2f32(<2 x float>, <2 x float>, <2 x float>) #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone speculatable }
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161
test/CodeGen/AMDGPU/mad-mix-lo.ll
Normal file
161
test/CodeGen/AMDGPU/mad-mix-lo.ll
Normal file
@ -0,0 +1,161 @@
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; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
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; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CIVI,VI %s
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; RUN: llc -march=amdgcn -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CIVI,CI %s
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; GCN-LABEL: mixlo_simple:
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; GCN: s_waitcnt
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; GFX9-NEXT: v_mad_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[0,0,0]{{$}}
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; GFX9-NEXT: s_setpc_b64
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; CIVI: v_mac_f32_e32
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; CIVI: v_cvt_f16_f32_e32
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define half @mixlo_simple(float %src0, float %src1, float %src2) #0 {
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%result = call float @llvm.fmuladd.f32(float %src0, float %src1, float %src2)
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%cvt.result = fptrunc float %result to half
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ret half %cvt.result
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}
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; GCN-LABEL: {{^}}v_mad_mixlo_f16_f16lo_f16lo_f16lo:
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; GFX9: v_mad_mixlo_f16 v0, v0, v1, v2{{$}}
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; CI: v_mac_f32
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; CIVI: v_cvt_f16_f32
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define half @v_mad_mixlo_f16_f16lo_f16lo_f16lo(half %src0, half %src1, half %src2) #0 {
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%src0.ext = fpext half %src0 to float
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%src1.ext = fpext half %src1 to float
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%src2.ext = fpext half %src2 to float
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%result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2.ext)
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%cvt.result = fptrunc float %result to half
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ret half %cvt.result
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}
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; GCN-LABEL: {{^}}v_mad_mixlo_f16_f16lo_f16lo_f32:
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; GCN: s_waitcnt
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; GFX9-NEXT: v_mad_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,0]{{$}}
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; GFX9-NEXT: s_setpc_b64
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; CIVI: v_mac_f32
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define half @v_mad_mixlo_f16_f16lo_f16lo_f32(half %src0, half %src1, float %src2) #0 {
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%src0.ext = fpext half %src0 to float
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%src1.ext = fpext half %src1 to float
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%result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2)
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%cvt.result = fptrunc float %result to half
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ret half %cvt.result
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}
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; GCN-LABEL: {{^}}v_mad_mixlo_f16_f16lo_f16lo_f32_clamp_post_cvt:
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; GCN: s_waitcnt
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; GFX9-NEXT: v_mad_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,0] clamp{{$}}
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; GFX9-NEXT: s_setpc_b64
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; CIVI: v_mac_f32_e32 v{{[0-9]}}, v{{[0-9]}}, v{{[0-9]$}}
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define half @v_mad_mixlo_f16_f16lo_f16lo_f32_clamp_post_cvt(half %src0, half %src1, float %src2) #0 {
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%src0.ext = fpext half %src0 to float
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%src1.ext = fpext half %src1 to float
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%result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2)
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%cvt.result = fptrunc float %result to half
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%max = call half @llvm.maxnum.f16(half %cvt.result, half 0.0)
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%clamp = call half @llvm.minnum.f16(half %max, half 1.0)
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ret half %clamp
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}
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; GCN-LABEL: {{^}}v_mad_mixlo_f16_f16lo_f16lo_f32_clamp_pre_cvt:
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; GCN: s_waitcnt
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; GFX9-NEXT: v_mad_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,0] clamp{{$}}
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; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0
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; GFX9-NEXT: s_setpc_b64
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; CIVI: v_mac_f32_e64 v{{[0-9]}}, v{{[0-9]}}, v{{[0-9]}} clamp{{$}}
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define half @v_mad_mixlo_f16_f16lo_f16lo_f32_clamp_pre_cvt(half %src0, half %src1, float %src2) #0 {
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%src0.ext = fpext half %src0 to float
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%src1.ext = fpext half %src1 to float
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%result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2)
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%max = call float @llvm.maxnum.f32(float %result, float 0.0)
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%clamp = call float @llvm.minnum.f32(float %max, float 1.0)
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%cvt.result = fptrunc float %clamp to half
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ret half %cvt.result
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}
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; GCN-LABEL: {{^}}v_mad_mixlo_v2f32:
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; GFX9: v_mad_mixlo_f16 v3, v0, v1, v2 op_sel:[1,1,1]
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; GFX9-NEXT: v_mad_mixlo_f16 v0, v0, v1, v2
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; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
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; GFX9-NEXT: v_lshl_or_b32 v0, v3, 16, v0
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; GFX9-NEXT: s_setpc_b64
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define <2 x half> @v_mad_mixlo_v2f32(<2 x half> %src0, <2 x half> %src1, <2 x half> %src2) #0 {
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%src0.ext = fpext <2 x half> %src0 to <2 x float>
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%src1.ext = fpext <2 x half> %src1 to <2 x float>
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%src2.ext = fpext <2 x half> %src2 to <2 x float>
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%result = tail call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %src0.ext, <2 x float> %src1.ext, <2 x float> %src2.ext)
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%cvt.result = fptrunc <2 x float> %result to <2 x half>
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ret <2 x half> %cvt.result
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}
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; GCN-LABEL: {{^}}v_mad_mixlo_v3f32:
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; GCN: s_waitcnt
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; GFX9-NEXT: v_mad_mixlo_f16 v0, v0, v3, v6
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; GFX9-NEXT: v_mad_mixlo_f16 v1, v1, v4, v7
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; GFX9-NEXT: v_mad_mixlo_f16 v2, v2, v5, v8
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; GFX9-NEXT: s_setpc_b64
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define <3 x half> @v_mad_mixlo_v3f32(<3 x half> %src0, <3 x half> %src1, <3 x half> %src2) #0 {
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%src0.ext = fpext <3 x half> %src0 to <3 x float>
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%src1.ext = fpext <3 x half> %src1 to <3 x float>
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%src2.ext = fpext <3 x half> %src2 to <3 x float>
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%result = tail call <3 x float> @llvm.fmuladd.v3f32(<3 x float> %src0.ext, <3 x float> %src1.ext, <3 x float> %src2.ext)
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%cvt.result = fptrunc <3 x float> %result to <3 x half>
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ret <3 x half> %cvt.result
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}
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; GCN-LABEL: {{^}}v_mad_mixlo_v4f32:
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; GCN: s_waitcnt
|
||||
; GFX9-NEXT: v_mad_mixlo_f16 v6, v0, v2, v4 op_sel:[1,1,1]
|
||||
; GFX9-NEXT: v_mad_mixlo_f16 v0, v0, v2, v4
|
||||
; GFX9-NEXT: v_mov_b32_e32 v2, 0xffff
|
||||
; GFX9-NEXT: v_mad_mixlo_f16 v4, v1, v3, v5 op_sel:[1,1,1]
|
||||
; GFX9-NEXT: v_mad_mixlo_f16 v1, v1, v3, v5
|
||||
; GFX9-NEXT: v_and_b32_e32 v0, v2, v0
|
||||
; GFX9-NEXT: v_and_b32_e32 v1, v2, v1
|
||||
; GFX9-NEXT: v_lshl_or_b32 v0, v6, 16, v0
|
||||
; GFX9-NEXT: v_lshl_or_b32 v1, v4, 16, v1
|
||||
; GFX9-NEXT: s_setpc_b64
|
||||
define <4 x half> @v_mad_mixlo_v4f32(<4 x half> %src0, <4 x half> %src1, <4 x half> %src2) #0 {
|
||||
%src0.ext = fpext <4 x half> %src0 to <4 x float>
|
||||
%src1.ext = fpext <4 x half> %src1 to <4 x float>
|
||||
%src2.ext = fpext <4 x half> %src2 to <4 x float>
|
||||
%result = tail call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %src0.ext, <4 x float> %src1.ext, <4 x float> %src2.ext)
|
||||
%cvt.result = fptrunc <4 x float> %result to <4 x half>
|
||||
ret <4 x half> %cvt.result
|
||||
}
|
||||
|
||||
; FIXME: Fold clamp
|
||||
; GCN-LABEL: {{^}}v_mad_mix_v2f32_clamp_postcvt:
|
||||
; GFX9: v_mad_mixlo_f16 v3, v0, v1, v2 op_sel:[1,1,1]
|
||||
; GFX9: v_mad_mixlo_f16 v0, v0, v1, v2
|
||||
; GFX9: v_lshl_or_b32 [[PACKED:v[0-9]+]]
|
||||
; GFX9: v_pk_max_f16 v0, [[PACKED]], [[PACKED]] clamp{{$}}
|
||||
; GFX9-NEXT: s_setpc_b64
|
||||
define <2 x half> @v_mad_mix_v2f32_clamp_postcvt(<2 x half> %src0, <2 x half> %src1, <2 x half> %src2) #0 {
|
||||
%src0.ext = fpext <2 x half> %src0 to <2 x float>
|
||||
%src1.ext = fpext <2 x half> %src1 to <2 x float>
|
||||
%src2.ext = fpext <2 x half> %src2 to <2 x float>
|
||||
%result = tail call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %src0.ext, <2 x float> %src1.ext, <2 x float> %src2.ext)
|
||||
%cvt.result = fptrunc <2 x float> %result to <2 x half>
|
||||
%max = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %cvt.result, <2 x half> zeroinitializer)
|
||||
%clamp = call <2 x half> @llvm.minnum.v2f16(<2 x half> %max, <2 x half> <half 1.0, half 1.0>)
|
||||
ret <2 x half> %clamp
|
||||
}
|
||||
|
||||
declare half @llvm.minnum.f16(half, half) #1
|
||||
declare <2 x half> @llvm.minnum.v2f16(<2 x half>, <2 x half>) #1
|
||||
|
||||
declare half @llvm.maxnum.f16(half, half) #1
|
||||
declare <2 x half> @llvm.maxnum.v2f16(<2 x half>, <2 x half>) #1
|
||||
|
||||
declare float @llvm.minnum.f32(float, float) #1
|
||||
declare float @llvm.maxnum.f32(float, float) #1
|
||||
declare float @llvm.fmuladd.f32(float, float, float) #1
|
||||
declare <2 x float> @llvm.fmuladd.v2f32(<2 x float>, <2 x float>, <2 x float>) #1
|
||||
declare <3 x float> @llvm.fmuladd.v3f32(<3 x float>, <3 x float>, <3 x float>) #1
|
||||
declare <4 x float> @llvm.fmuladd.v4f32(<4 x float>, <4 x float>, <4 x float>) #1
|
||||
|
||||
attributes #0 = { nounwind }
|
||||
attributes #1 = { nounwind readnone speculatable }
|
||||
Loading…
Reference in New Issue
Block a user