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Don't create neon moves in CopyRegToReg. NEONMoveFixPass will do the conversion
if profitable. llvm-svn: 107673
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@ -718,6 +718,12 @@ ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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if (SrcRC == ARM::DPR_8RegisterClass)
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SrcRC = ARM::DPR_VFP2RegisterClass;
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// NEONMoveFixPass will convert VFP moves to NEON moves when profitable.
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if (DestRC == ARM::DPR_VFP2RegisterClass)
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DestRC = ARM::DPRRegisterClass;
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if (SrcRC == ARM::DPR_VFP2RegisterClass)
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SrcRC = ARM::DPRRegisterClass;
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// Allow QPR / QPR_VFP2 / QPR_8 cross-class copies.
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if (DestRC == ARM::QPR_VFP2RegisterClass ||
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DestRC == ARM::QPR_8RegisterClass)
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@ -750,10 +756,6 @@ ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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Opc = (SrcRC == ARM::GPRRegisterClass ? ARM::VMOVSR : ARM::VMOVS);
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else if (DestRC == ARM::DPRRegisterClass)
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Opc = ARM::VMOVD;
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else if (DestRC == ARM::DPR_VFP2RegisterClass ||
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SrcRC == ARM::DPR_VFP2RegisterClass)
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// Always use neon reg-reg move if source or dest is NEON-only regclass.
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Opc = ARM::VMOVDneon;
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else if (DestRC == ARM::QPRRegisterClass)
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Opc = ARM::VMOVQ;
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else if (DestRC == ARM::QQPRRegisterClass)
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@ -205,7 +205,7 @@ define <4 x i32> @vsetQ_lane32(<4 x i32>* %A, i32 %B) nounwind {
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define arm_aapcs_vfpcc <2 x float> @test_vset_lanef32(float %arg0_float32_t, <2 x float> %arg1_float32x2_t) nounwind {
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;CHECK: test_vset_lanef32:
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;CHECK: vmov.f32 s3, s0
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;CHECK: vmov d0, d1
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;CHECK: vmov.f64 d0, d1
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entry:
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%0 = insertelement <2 x float> %arg1_float32x2_t, float %arg0_float32_t, i32 1 ; <<2 x float>> [#uses=1]
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ret <2 x float> %0
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