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Don't create neon moves in CopyRegToReg. NEONMoveFixPass will do the conversion

if profitable.

llvm-svn: 107673
This commit is contained in:
Rafael Espindola 2010-07-06 16:24:34 +00:00
parent 18ba4703b0
commit e5689571a1
2 changed files with 7 additions and 5 deletions

View File

@ -718,6 +718,12 @@ ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
if (SrcRC == ARM::DPR_8RegisterClass)
SrcRC = ARM::DPR_VFP2RegisterClass;
// NEONMoveFixPass will convert VFP moves to NEON moves when profitable.
if (DestRC == ARM::DPR_VFP2RegisterClass)
DestRC = ARM::DPRRegisterClass;
if (SrcRC == ARM::DPR_VFP2RegisterClass)
SrcRC = ARM::DPRRegisterClass;
// Allow QPR / QPR_VFP2 / QPR_8 cross-class copies.
if (DestRC == ARM::QPR_VFP2RegisterClass ||
DestRC == ARM::QPR_8RegisterClass)
@ -750,10 +756,6 @@ ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
Opc = (SrcRC == ARM::GPRRegisterClass ? ARM::VMOVSR : ARM::VMOVS);
else if (DestRC == ARM::DPRRegisterClass)
Opc = ARM::VMOVD;
else if (DestRC == ARM::DPR_VFP2RegisterClass ||
SrcRC == ARM::DPR_VFP2RegisterClass)
// Always use neon reg-reg move if source or dest is NEON-only regclass.
Opc = ARM::VMOVDneon;
else if (DestRC == ARM::QPRRegisterClass)
Opc = ARM::VMOVQ;
else if (DestRC == ARM::QQPRRegisterClass)

View File

@ -205,7 +205,7 @@ define <4 x i32> @vsetQ_lane32(<4 x i32>* %A, i32 %B) nounwind {
define arm_aapcs_vfpcc <2 x float> @test_vset_lanef32(float %arg0_float32_t, <2 x float> %arg1_float32x2_t) nounwind {
;CHECK: test_vset_lanef32:
;CHECK: vmov.f32 s3, s0
;CHECK: vmov d0, d1
;CHECK: vmov.f64 d0, d1
entry:
%0 = insertelement <2 x float> %arg1_float32x2_t, float %arg0_float32_t, i32 1 ; <<2 x float>> [#uses=1]
ret <2 x float> %0