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[VE] Implements minimum MC layer for VE (1/4)
Summary: Correct instruction bitfield addresses to generate machine code correctly. Also add some variables to represent all instructions correctly and change default values to use registers by default. Differential Revision: https://reviews.llvm.org/D79539
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@ -6,6 +6,20 @@
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//
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//===----------------------------------------------------------------------===//
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// SX-Aurora uses little endian, but instructions are encoded little bit
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// different manner. Therefore, we need to tranlate the address of each
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// bitfield described in ISA documentation like below.
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//
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// ISA | InstrFormats.td
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// ---------------------------
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// 0-7 => 63-56
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// 8 => 55
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// 32-63 => 31-0
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//===----------------------------------------------------------------------===//
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// Instruction Format
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//===----------------------------------------------------------------------===//
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class InstVE<dag outs, dag ins, string asmstr, list<dag> pattern>
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: Instruction {
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field bits<64> Inst;
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@ -14,7 +28,7 @@ class InstVE<dag outs, dag ins, string asmstr, list<dag> pattern>
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let Size = 8;
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bits<8> op;
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let Inst{0-7} = op;
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let Inst{63-56} = op;
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dag OutOperandList = outs;
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dag InOperandList = ins;
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@ -25,50 +39,114 @@ class InstVE<dag outs, dag ins, string asmstr, list<dag> pattern>
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field bits<64> SoftFail = 0;
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}
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class RM<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern=[]>
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//-----------------------------------------------------------------------------
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// Section 5.1 RM Type
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//
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// RM type has sx, sy, sz, and imm32.
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// The effective address is generated by sz + sy + imm32.
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//-----------------------------------------------------------------------------
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class RM<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern = []>
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: InstVE<outs, ins, asmstr, pattern> {
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bits<1> cx = 0;
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bits<7> sx;
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bits<1> cy = 0;
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bits<1> cy = 1;
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bits<7> sz; // defines sz prior to sy to assign from sz
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bits<7> sy;
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bits<1> cz = 0;
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bits<7> sz;
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bits<32> imm32 = 0;
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bits<1> cz = 1;
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bits<32> imm32;
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let op = opVal;
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let Inst{15} = cx;
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let Inst{14-8} = sx;
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let Inst{23} = cy;
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let Inst{22-16} = sy;
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let Inst{31} = cz;
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let Inst{30-24} = sz;
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let Inst{63-32} = imm32;
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let Inst{55} = cx;
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let Inst{54-48} = sx;
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let Inst{47} = cy;
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let Inst{46-40} = sy;
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let Inst{39} = cz;
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let Inst{38-32} = sz;
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let Inst{31-0} = imm32;
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}
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class RR<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern=[]>
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: RM<opVal, outs, ins, asmstr, pattern> {
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//-----------------------------------------------------------------------------
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// Section 5.2 RRM Type
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// Section 5.3 CF Type
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//
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// CF type is used for control flow.
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//-----------------------------------------------------------------------------
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class CF<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern = []>
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: InstVE<outs, ins, asmstr, pattern> {
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bits<1> cx = 0;
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bits<1> cx2 = 0;
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bits<2> bpf = 0;
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bits<4> cf;
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bits<1> cy = 1;
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bits<7> sy;
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bits<1> cz = 1;
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bits<7> sz;
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bits<32> imm32;
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let op = opVal;
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let Inst{55} = cx;
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let Inst{54} = cx2;
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let Inst{53-52} = bpf;
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let Inst{51-48} = cf;
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let Inst{47} = cy;
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let Inst{46-40} = sy;
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let Inst{39} = cz;
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let Inst{38-32} = sz;
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let Inst{31-0} = imm32;
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}
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//-----------------------------------------------------------------------------
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// Section 5.4 RR Type
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//
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// RR type is for generic arithmetic instructions.
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//-----------------------------------------------------------------------------
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class RR<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern = []>
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: InstVE<outs, ins, asmstr, pattern> {
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bits<1> cx = 0;
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bits<7> sx;
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bits<1> cy = 1;
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bits<7> sy;
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bits<1> cz = 1;
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bits<7> sz; // m field places at the top sz field
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bits<8> vx = 0;
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bits<8> vz = 0;
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bits<1> cw = 0;
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bits<1> cw2 = 0;
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bits<4> cfw = 0;
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let imm32{0-23} = 0;
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let imm32{24} = cw;
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let imm32{25} = cw2;
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let imm32{26-27} = 0;
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let imm32{28-31} = cfw;
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let op = opVal;
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let Inst{55} = cx;
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let Inst{54-48} = sx;
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let Inst{47} = cy;
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let Inst{46-40} = sy;
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let Inst{39} = cz;
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let Inst{38-32} = sz;
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let Inst{31-24} = vx;
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let Inst{23-16} = 0;
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let Inst{15-8} = vz;
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let Inst{7} = cw;
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let Inst{6} = cw2;
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let Inst{5-4} = 0;
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let Inst{3-0} = cfw;
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}
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class CF<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern=[]>
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: RM<opVal, outs, ins, asmstr, pattern> {
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bits<1> cx2;
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bits<2> bpf;
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bits<4> cf;
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let cx = 0;
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let sx{6} = cx2;
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let sx{5-4} = bpf;
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let sx{3-0} = cf;
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}
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//-----------------------------------------------------------------------------
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// Section 5.5 RW Type
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// Section 5.6 RVM Type
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// Section 5.7 RV Type
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//-----------------------------------------------------------------------------
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// Pseudo instructions.
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class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern=[]>
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class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern = []>
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: InstVE<outs, ins, asmstr, pattern> {
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let isCodeGenOnly = 1;
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let isPseudo = 1;
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