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[VE] Implements minimum MC layer for VE (1/4)

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Summary:
Correct instruction bitfield addresses to generate machine code correctly.  Also
add some variables to represent all instructions correctly and change default
values to use registers by default.

Differential Revision: https://reviews.llvm.org/D79539
This commit is contained in:
Kazushi (Jam) Marukawa 2020-05-07 13:10:02 +02:00 committed by Simon Moll
parent 9c1ea50dad
commit e5e1ae146f
1 changed files with 109 additions and 31 deletions
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140
lib/Target/VE/VEInstrFormats.td
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@ -6,6 +6,20 @@
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// SX-Aurora uses little endian, but instructions are encoded little bit
// different manner. Therefore, we need to tranlate the address of each
// bitfield described in ISA documentation like below.
//
// ISA | InstrFormats.td
// ---------------------------
// 0-7 => 63-56
// 8 => 55
// 32-63 => 31-0
//===----------------------------------------------------------------------===//
// Instruction Format
//===----------------------------------------------------------------------===//
class InstVE<dag outs, dag ins, string asmstr, list<dag> pattern> class InstVE<dag outs, dag ins, string asmstr, list<dag> pattern>
: Instruction { : Instruction {
field bits<64> Inst; field bits<64> Inst;
@ -14,7 +28,7 @@ class InstVE<dag outs, dag ins, string asmstr, list<dag> pattern>
let Size = 8; let Size = 8;
bits<8> op; bits<8> op;
let Inst{0-7} = op; let Inst{63-56} = op;
dag OutOperandList = outs; dag OutOperandList = outs;
dag InOperandList = ins; dag InOperandList = ins;
@ -25,50 +39,114 @@ class InstVE<dag outs, dag ins, string asmstr, list<dag> pattern>
field bits<64> SoftFail = 0; field bits<64> SoftFail = 0;
} }
class RM<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern=[]> //-----------------------------------------------------------------------------
// Section 5.1 RM Type
//
// RM type has sx, sy, sz, and imm32.
// The effective address is generated by sz + sy + imm32.
//-----------------------------------------------------------------------------
class RM<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern = []>
: InstVE<outs, ins, asmstr, pattern> { : InstVE<outs, ins, asmstr, pattern> {
bits<1> cx = 0; bits<1> cx = 0;
bits<7> sx; bits<7> sx;
bits<1> cy = 0; bits<1> cy = 1;
bits<7> sz; // defines sz prior to sy to assign from sz
bits<7> sy; bits<7> sy;
bits<1> cz = 0; bits<1> cz = 1;
bits<7> sz; bits<32> imm32;
bits<32> imm32 = 0;
let op = opVal; let op = opVal;
let Inst{15} = cx; let Inst{55} = cx;
let Inst{14-8} = sx; let Inst{54-48} = sx;
let Inst{23} = cy; let Inst{47} = cy;
let Inst{22-16} = sy; let Inst{46-40} = sy;
let Inst{31} = cz; let Inst{39} = cz;
let Inst{30-24} = sz; let Inst{38-32} = sz;
let Inst{63-32} = imm32; let Inst{31-0} = imm32;
} }
class RR<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern=[]> //-----------------------------------------------------------------------------
: RM<opVal, outs, ins, asmstr, pattern> { // Section 5.2 RRM Type
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Section 5.3 CF Type
//
// CF type is used for control flow.
//-----------------------------------------------------------------------------
class CF<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern = []>
: InstVE<outs, ins, asmstr, pattern> {
bits<1> cx = 0;
bits<1> cx2 = 0;
bits<2> bpf = 0;
bits<4> cf;
bits<1> cy = 1;
bits<7> sy;
bits<1> cz = 1;
bits<7> sz;
bits<32> imm32;
let op = opVal;
let Inst{55} = cx;
let Inst{54} = cx2;
let Inst{53-52} = bpf;
let Inst{51-48} = cf;
let Inst{47} = cy;
let Inst{46-40} = sy;
let Inst{39} = cz;
let Inst{38-32} = sz;
let Inst{31-0} = imm32;
}
//-----------------------------------------------------------------------------
// Section 5.4 RR Type
//
// RR type is for generic arithmetic instructions.
//-----------------------------------------------------------------------------
class RR<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern = []>
: InstVE<outs, ins, asmstr, pattern> {
bits<1> cx = 0;
bits<7> sx;
bits<1> cy = 1;
bits<7> sy;
bits<1> cz = 1;
bits<7> sz; // m field places at the top sz field
bits<8> vx = 0;
bits<8> vz = 0;
bits<1> cw = 0; bits<1> cw = 0;
bits<1> cw2 = 0; bits<1> cw2 = 0;
bits<4> cfw = 0; bits<4> cfw = 0;
let imm32{0-23} = 0; let op = opVal;
let imm32{24} = cw; let Inst{55} = cx;
let imm32{25} = cw2; let Inst{54-48} = sx;
let imm32{26-27} = 0; let Inst{47} = cy;
let imm32{28-31} = cfw; let Inst{46-40} = sy;
let Inst{39} = cz;
let Inst{38-32} = sz;
let Inst{31-24} = vx;
let Inst{23-16} = 0;
let Inst{15-8} = vz;
let Inst{7} = cw;
let Inst{6} = cw2;
let Inst{5-4} = 0;
let Inst{3-0} = cfw;
} }
class CF<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern=[]> //-----------------------------------------------------------------------------
: RM<opVal, outs, ins, asmstr, pattern> { // Section 5.5 RW Type
bits<1> cx2; //-----------------------------------------------------------------------------
bits<2> bpf;
bits<4> cf; //-----------------------------------------------------------------------------
let cx = 0; // Section 5.6 RVM Type
let sx{6} = cx2; //-----------------------------------------------------------------------------
let sx{5-4} = bpf;
let sx{3-0} = cf; //-----------------------------------------------------------------------------
} // Section 5.7 RV Type
//-----------------------------------------------------------------------------
// Pseudo instructions. // Pseudo instructions.
class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern=[]> class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern = []>
: InstVE<outs, ins, asmstr, pattern> { : InstVE<outs, ins, asmstr, pattern> {
let isCodeGenOnly = 1; let isCodeGenOnly = 1;
let isPseudo = 1; let isPseudo = 1;