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Revert "[AArch64] This is a work in progress to provide a machine description"
This reverts commit ff717c8fc786a0cfa1602982b91895fa09e514fc. llvm-svn: 202773
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Chad Rosier
parent
cef5500602
commit
e60c767814
@ -41,20 +41,13 @@ class ProcNoItin<string Name, list<SubtargetFeature> Features>
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def : Processor<"generic", GenericItineraries, [FeatureFPARMv8, FeatureNEON]>;
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def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
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"Cortex-A53 ARM processors",
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[FeatureFPARMv8,
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FeatureNEON,
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FeatureCrypto]>;
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def : ProcNoItin<"cortex-a53", [FeatureFPARMv8,
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FeatureNEON,
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FeatureCrypto]>;
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def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
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"Cortex-A57 ARM processors",
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[FeatureFPARMv8,
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FeatureNEON,
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FeatureCrypto]>;
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def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
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def : Processor<"cortex-a57", NoItineraries, [ProcA57]>;
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def : ProcNoItin<"cortex-a57", [FeatureFPARMv8,
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FeatureNEON,
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FeatureCrypto]>;
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//===----------------------------------------------------------------------===//
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// Register File Description
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File diff suppressed because it is too large
Load Diff
@ -7,66 +7,4 @@
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Generic processor itineraries for legacy compatibility.
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def GenericItineraries : ProcessorItineraries<[], [], []>;
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//===----------------------------------------------------------------------===//
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// Base SchedReadWrite types
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// Basic ALU
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def WriteALU : SchedWrite; // Generic: may contain shift and/or ALU operation
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def WriteALUs : SchedWrite; // Shift only with no ALU operation
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def ReadALU : SchedRead; // Operand not needed for shifting
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def ReadALUs : SchedRead; // Operand needed for shifting
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// Multiply with optional accumulate
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def WriteMAC : SchedWrite;
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def ReadMAC : SchedRead;
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// Compares
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def WriteCMP : SchedWrite;
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def ReadCMP : SchedRead;
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// Division
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def WriteDiv : SchedWrite;
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def ReadDiv : SchedRead;
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// Loads
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def WriteLd : SchedWrite;
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def WritePreLd : SchedWrite;
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def ReadLd : SchedRead;
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def ReadPreLd : SchedRead;
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// Branches
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def WriteBr : SchedWrite;
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def WriteBrL : SchedWrite;
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def ReadBr : SchedRead;
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// Floating Point ALU
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def WriteFPALU : SchedWrite;
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def ReadFPALU : SchedRead;
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// Floating Point MAC, Mul, Div, Sqrt
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// Most processors will simply send all of these down a dedicated pipe, but
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// they're explicitly seperated here for flexibility of modeling later. May
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// consider consolidating them into a single WriteFPXXXX type in the future.
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def WriteFPMAC : SchedWrite;
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def WriteFPMul : SchedWrite;
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def WriteFPDiv : SchedWrite;
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def WriteFPSqrt : SchedWrite;
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def ReadFPMAC : SchedRead;
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def ReadFPMul : SchedRead;
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def ReadFPDiv : SchedRead;
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def ReadFPSqrt : SchedRead;
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// Noop
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def WriteNoop : SchedWrite;
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//===----------------------------------------------------------------------===//
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// Subtarget specific Machine Models.
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include "AArch64ScheduleA53.td"
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@ -1,130 +0,0 @@
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//=- AArch64ScheduleA53.td - ARM Cortex-A53 Scheduling Definitions -*- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the itinerary class data for the ARM Cortex A53 processors.
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//
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//===----------------------------------------------------------------------===//
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// ===---------------------------------------------------------------------===//
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// The following definitions describe the simpler per-operand machine model.
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// This works with MachineScheduler. See MCSchedModel.h for details.
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// Cortex-A53 machine model for scheduling and other instruction cost heuristics.
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def CortexA53Model : SchedMachineModel {
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let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.
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let MinLatency = 1 ; // OperandCycles are interpreted as MinLatency.
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let LoadLatency = 2; // Optimistic load latency assuming bypass.
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// This is overriden by OperandCycles if the
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// Itineraries are queried instead.
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let MispredictPenalty = 9; // Based on "Cortex-A53 Software Optimisation
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// Specification - Instruction Timings"
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// v 1.0 Spreadsheet
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}
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//===----------------------------------------------------------------------===//
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// Define each kind of processor resource and number available.
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// Modeling each pipeline as a ProcResource using the default BufferSize = -1.
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// Cortex-A53 is in-order and therefore should be using BufferSize = 0. The
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// current configuration performs better with the basic latencies provided so
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// far. Will revisit BufferSize once the latency information is more accurate.
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let SchedModel = CortexA53Model in {
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def A53UnitALU : ProcResource<2>; // Int ALU
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def A53UnitMAC : ProcResource<1>; // Int MAC
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def A53UnitDiv : ProcResource<1>; // Int Division
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def A53UnitLdSt : ProcResource<1>; // Load/Store
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def A53UnitB : ProcResource<1>; // Branch
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def A53UnitFPALU : ProcResource<1>; // FP ALU
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def A53UnitFPMDS : ProcResource<1>; // FP Mult/Div/Sqrt
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//===----------------------------------------------------------------------===//
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// Subtarget-specific SchedWrite types which both map the ProcResources and
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// set the latency.
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// Issue - Every instruction must consume an A53WriteIssue. Optionally,
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// instructions that cannot be dual-issued will also include the
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// A53WriteIssue2nd in their SchedRW list. That second WriteRes will
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// ensure that a second issue slot is consumed.
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def A53WriteIssue : SchedWriteRes<[]>;
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def A53WriteIssue2nd : SchedWriteRes<[]> { let Latency = 0; }
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// ALU - These are reduced to 1 despite a true latency of 4 in order to easily
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// model forwarding logic. Once forwarding is properly modelled, then
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// they'll be corrected.
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def : WriteRes<WriteALU, [A53UnitALU]> { let Latency = 1; }
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def : WriteRes<WriteALUs, [A53UnitALU]> { let Latency = 1; }
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def : WriteRes<WriteCMP, [A53UnitALU]> { let Latency = 1; }
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// MAC
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def : WriteRes<WriteMAC, [A53UnitMAC]> { let Latency = 4; }
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// Div
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def : WriteRes<WriteDiv, [A53UnitDiv]> { let Latency = 4; }
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// Load
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def : WriteRes<WriteLd, [A53UnitLdSt]> { let Latency = 4; }
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def : WriteRes<WritePreLd, [A53UnitLdSt]> { let Latency = 4; }
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// Branch
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def : WriteRes<WriteBr, [A53UnitB]>;
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def : WriteRes<WriteBrL, [A53UnitB]>;
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// FP ALU
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def : WriteRes<WriteFPALU, [A53UnitFPALU]> {let Latency = 6; }
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// FP MAC, Mul, Div, Sqrt
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// Using Double Precision numbers for now as a worst case. Additionally, not
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// modeling the exact hazard but instead treating the whole pipe as a hazard.
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// As an example VMUL, VMLA, and others are actually pipelined. VDIV and VSQRT
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// have a total latency of 33 and 32 respectively but only a hazard of 29 and
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// 28 (double-prescion example).
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def : WriteRes<WriteFPMAC, [A53UnitFPMDS]> { let Latency = 10; }
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def : WriteRes<WriteFPMul, [A53UnitFPMDS]> { let Latency = 6; }
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def : WriteRes<WriteFPDiv, [A53UnitFPMDS]> { let Latency = 33;
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let ResourceCycles = [29]; }
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def : WriteRes<WriteFPSqrt, [A53UnitFPMDS]> { let Latency = 32;
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let ResourceCycles = [28]; }
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//===----------------------------------------------------------------------===//
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// Subtarget-specific SchedRead types.
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// No forwarding defined for ReadALU yet.
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def : ReadAdvance<ReadALU, 0>;
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// No forwarding defined for ReadCMP yet.
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def : ReadAdvance<ReadCMP, 0>;
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// No forwarding defined for ReadBr yet.
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def : ReadAdvance<ReadBr, 0>;
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// No forwarding defined for ReadMAC yet.
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def : ReadAdvance<ReadMAC, 0>;
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// No forwarding defined for ReadDiv yet.
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def : ReadAdvance<ReadDiv, 0>;
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// No forwarding defined for ReadLd, ReadPreLd yet.
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def : ReadAdvance<ReadLd, 0>;
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def : ReadAdvance<ReadPreLd, 0>;
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// No forwarding defined for ReadFPALU yet.
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def : ReadAdvance<ReadFPALU, 0>;
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// No forwarding defined for ReadFPMAC/Mul/Div/Sqrt yet.
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def : ReadAdvance<ReadFPMAC, 0>;
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def : ReadAdvance<ReadFPMul, 0>;
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def : ReadAdvance<ReadFPDiv, 0>;
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def : ReadAdvance<ReadFPSqrt, 0>;
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}
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@ -29,11 +29,6 @@ class GlobalValue;
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class AArch64Subtarget : public AArch64GenSubtargetInfo {
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virtual void anchor();
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protected:
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enum ARMProcFamilyEnum {Others, CortexA53, CortexA57};
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/// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
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ARMProcFamilyEnum ARMProcFamily;
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bool HasFPARMv8;
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bool HasNEON;
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bool HasCrypto;
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@ -1,83 +0,0 @@
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; REQUIRES: asserts
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; RUN: llc < %s -march=aarch64 -mcpu=cortex-a53 -pre-RA-sched=source -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s
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;
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; The Cortex-A53 machine model will cause the MADD instruction to be scheduled
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; much higher than the ADD instructions in order to hide latency. When not
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; specifying a subtarget, the MADD will remain near the end of the block.
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; CHECK: main
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; CHECK: *** Final schedule for BB#2 ***
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; CHECK: SU(13)
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; CHECK: MADDwwww
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; CHECK: SU(4)
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; CHECK: ADDwwi_lsl0_s
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; CHECK: ********** MI Scheduling **********
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@main.x = private unnamed_addr constant [8 x i32] [i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1], align 4
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@main.y = private unnamed_addr constant [8 x i32] [i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2], align 4
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; Function Attrs: nounwind
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define i32 @main() #0 {
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entry:
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%retval = alloca i32, align 4
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%x = alloca [8 x i32], align 4
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%y = alloca [8 x i32], align 4
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%i = alloca i32, align 4
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%xx = alloca i32, align 4
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%yy = alloca i32, align 4
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store i32 0, i32* %retval
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%0 = bitcast [8 x i32]* %x to i8*
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call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* bitcast ([8 x i32]* @main.x to i8*), i64 32, i32 4, i1 false)
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%1 = bitcast [8 x i32]* %y to i8*
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call void @llvm.memcpy.p0i8.p0i8.i64(i8* %1, i8* bitcast ([8 x i32]* @main.y to i8*), i64 32, i32 4, i1 false)
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store i32 0, i32* %xx, align 4
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store i32 0, i32* %yy, align 4
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store i32 0, i32* %i, align 4
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br label %for.cond
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for.cond: ; preds = %for.inc, %entry
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%2 = load i32* %i, align 4
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%cmp = icmp slt i32 %2, 8
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br i1 %cmp, label %for.body, label %for.end
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for.body: ; preds = %for.cond
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%3 = load i32* %i, align 4
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%idxprom = sext i32 %3 to i64
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%arrayidx = getelementptr inbounds [8 x i32]* %x, i32 0, i64 %idxprom
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%4 = load i32* %arrayidx, align 4
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%add = add nsw i32 %4, 1
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store i32 %add, i32* %xx, align 4
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%5 = load i32* %xx, align 4
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%add1 = add nsw i32 %5, 12
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store i32 %add1, i32* %xx, align 4
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%6 = load i32* %xx, align 4
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%add2 = add nsw i32 %6, 23
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store i32 %add2, i32* %xx, align 4
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%7 = load i32* %xx, align 4
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%add3 = add nsw i32 %7, 34
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store i32 %add3, i32* %xx, align 4
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%8 = load i32* %i, align 4
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%idxprom4 = sext i32 %8 to i64
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%arrayidx5 = getelementptr inbounds [8 x i32]* %y, i32 0, i64 %idxprom4
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%9 = load i32* %arrayidx5, align 4
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%10 = load i32* %yy, align 4
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%mul = mul nsw i32 %10, %9
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store i32 %mul, i32* %yy, align 4
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br label %for.inc
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for.inc: ; preds = %for.body
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%11 = load i32* %i, align 4
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%inc = add nsw i32 %11, 1
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store i32 %inc, i32* %i, align 4
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br label %for.cond
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for.end: ; preds = %for.cond
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%12 = load i32* %xx, align 4
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%13 = load i32* %yy, align 4
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%add6 = add nsw i32 %12, %13
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ret i32 %add6
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}
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; Function Attrs: nounwind
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declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i32, i1) #1
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attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
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attributes #1 = { nounwind }
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