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[ARM] Add macro fusion for AES instructions.
Summary: This patch adds a macro fusion using CodeGen/MacroFusion.cpp to pair AES instructions back to back and adds FeatureFuseAES to enable the feature. Reviewers: evandro, javed.absar, rengolin, t.p.northover Reviewed By: javed.absar Subscribers: aemerson, mgorny, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D34142 llvm-svn: 305988
This commit is contained in:
Florian Hahn
parent
29f38846f1
commit
e66623c920
@ -100,7 +100,8 @@ def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true",
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"Enable Reliability, Availability and Serviceability extensions">;
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def FeatureFPAO : SubtargetFeature<"fpao", "HasFPAO", "true",
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"Enable fast computation of positive address offsets">;
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def FeatureFuseAES : SubtargetFeature<"fuse-aes", "HasFuseAES", "true",
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"CPU fuses AES crypto operations">;
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// Cyclone has preferred instructions for zeroing VFP registers, which can
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// execute in 0 cycles.
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57
lib/Target/ARM/ARMMacroFusion.cpp
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57
lib/Target/ARM/ARMMacroFusion.cpp
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@ -0,0 +1,57 @@
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//===- ARMMacroFusion.cpp - ARM Macro Fusion ----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file This file contains the ARM implementation of the DAG scheduling
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/// mutation to pair instructions back to back.
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//
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//===----------------------------------------------------------------------===//
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#include "ARMMacroFusion.h"
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#include "ARMSubtarget.h"
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#include "llvm/CodeGen/MacroFusion.h"
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#include "llvm/Target/TargetInstrInfo.h"
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namespace llvm {
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/// \brief Check if the instr pair, FirstMI and SecondMI, should be fused
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/// together. Given SecondMI, when FirstMI is unspecified, then check if
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/// SecondMI may be part of a fused pair at all.
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static bool shouldScheduleAdjacent(const TargetInstrInfo &TII,
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const TargetSubtargetInfo &TSI,
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const MachineInstr *FirstMI,
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const MachineInstr &SecondMI) {
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const ARMSubtarget &ST = static_cast<const ARMSubtarget&>(TSI);
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// Assume wildcards for unspecified instrs.
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unsigned FirstOpcode =
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FirstMI ? FirstMI->getOpcode()
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: static_cast<unsigned>(ARM::INSTRUCTION_LIST_END);
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unsigned SecondOpcode = SecondMI.getOpcode();
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if (ST.hasFuseAES())
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// Fuse AES crypto operations.
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switch(SecondOpcode) {
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// AES encode.
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case ARM::AESMC :
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return FirstOpcode == ARM::AESE ||
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FirstOpcode == ARM::INSTRUCTION_LIST_END;
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// AES decode.
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case ARM::AESIMC:
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return FirstOpcode == ARM::AESD ||
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FirstOpcode == ARM::INSTRUCTION_LIST_END;
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}
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return false;
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}
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std::unique_ptr<ScheduleDAGMutation> createARMMacroFusionDAGMutation () {
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return createMacroFusionDAGMutation(shouldScheduleAdjacent);
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}
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} // end namespace llvm
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24
lib/Target/ARM/ARMMacroFusion.h
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24
lib/Target/ARM/ARMMacroFusion.h
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@ -0,0 +1,24 @@
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//===- ARMMacroFusion.h - ARM Macro Fusion ------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file This file contains the ARM definition of the DAG scheduling mutation
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/// to pair instructions back to back.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/MachineScheduler.h"
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namespace llvm {
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/// Note that you have to add:
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/// DAG.addMutation(createARMMacroFusionDAGMutation());
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/// to ARMPassConfig::createMachineScheduler() to have an effect.
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std::unique_ptr<ScheduleDAGMutation> createARMMacroFusionDAGMutation();
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} // llvm
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@ -285,6 +285,10 @@ protected:
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/// HasFPAO - if true, processor does positive address offset computation faster
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bool HasFPAO = false;
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/// HasFuseAES - if true, processor executes back to back AES instruction
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/// pairs faster.
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bool HasFuseAES = false;
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/// If true, if conversion may decide to leave some instructions unpredicated.
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bool IsProfitableToUnpredicate = false;
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@ -561,6 +565,10 @@ public:
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bool hasD16() const { return HasD16; }
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bool hasFullFP16() const { return HasFullFP16; }
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bool hasFuseAES() const { return HasFuseAES; }
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/// \brief Return true if the CPU supports any kind of instruction fusion.
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bool hasFusion() const { return hasFuseAES(); }
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const Triple &getTargetTriple() const { return TargetTriple; }
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bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
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@ -17,6 +17,7 @@
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#include "ARMRegisterBankInfo.h"
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#endif
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#include "ARMSubtarget.h"
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#include "ARMMacroFusion.h"
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#include "ARMTargetMachine.h"
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#include "ARMTargetObjectFile.h"
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#include "ARMTargetTransformInfo.h"
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@ -394,6 +395,9 @@ public:
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createMachineScheduler(MachineSchedContext *C) const override {
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ScheduleDAGMILive *DAG = createGenericSchedLive(C);
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// add DAG Mutations here.
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const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
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if (ST.hasFusion())
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DAG->addMutation(createARMMacroFusionDAGMutation());
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return DAG;
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}
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@ -401,6 +405,9 @@ public:
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createPostMachineScheduler(MachineSchedContext *C) const override {
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ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
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// add DAG Mutations here.
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const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
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if (ST.hasFusion())
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DAG->addMutation(createARMMacroFusionDAGMutation());
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return DAG;
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}
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@ -49,6 +49,7 @@ add_llvm_target(ARMCodeGen
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ARMLoadStoreOptimizer.cpp
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ARMMCInstLower.cpp
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ARMMachineFunctionInfo.cpp
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ARMMacroFusion.cpp
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ARMRegisterInfo.cpp
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ARMOptimizeBarriersPass.cpp
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ARMSelectionDAGInfo.cpp
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203
test/CodeGen/ARM/misched-fusion-aes.ll
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203
test/CodeGen/ARM/misched-fusion-aes.ll
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@ -0,0 +1,203 @@
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; RUN: llc %s -o - -mtriple=armv8 -mattr=+crypto,+fuse-aes -enable-misched -disable-post-ra | FileCheck %s
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declare <16 x i8> @llvm.arm.neon.aese(<16 x i8> %d, <16 x i8> %k)
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declare <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %d)
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declare <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %d, <16 x i8> %k)
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declare <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %d)
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define void @aesea(<16 x i8>* %a0, <16 x i8>* %b0, <16 x i8>* %c0, <16 x i8> %d, <16 x i8> %e) {
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%d0 = load <16 x i8>, <16 x i8>* %a0
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%a1 = getelementptr inbounds <16 x i8>, <16 x i8>* %a0, i64 1
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%d1 = load <16 x i8>, <16 x i8>* %a1
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%a2 = getelementptr inbounds <16 x i8>, <16 x i8>* %a0, i64 2
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%d2 = load <16 x i8>, <16 x i8>* %a2
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%a3 = getelementptr inbounds <16 x i8>, <16 x i8>* %a0, i64 3
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%d3 = load <16 x i8>, <16 x i8>* %a3
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%k0 = load <16 x i8>, <16 x i8>* %b0
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%e00 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %d0, <16 x i8> %k0)
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%f00 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %e00)
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%e01 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %d1, <16 x i8> %k0)
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%f01 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %e01)
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%e02 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %d2, <16 x i8> %k0)
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%f02 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %e02)
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%e03 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %d3, <16 x i8> %k0)
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%f03 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %e03)
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%b1 = getelementptr inbounds <16 x i8>, <16 x i8>* %b0, i64 1
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%k1 = load <16 x i8>, <16 x i8>* %b1
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%e10 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %f00, <16 x i8> %k1)
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%f10 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %e00)
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%e11 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %f01, <16 x i8> %k1)
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%f11 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %e01)
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%e12 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %f02, <16 x i8> %k1)
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%f12 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %e02)
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%e13 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %f03, <16 x i8> %k1)
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%f13 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %e03)
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%b2 = getelementptr inbounds <16 x i8>, <16 x i8>* %b0, i64 2
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%k2 = load <16 x i8>, <16 x i8>* %b2
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%e20 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %f10, <16 x i8> %k2)
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%f20 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %e10)
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%e21 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %f11, <16 x i8> %k2)
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%f21 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %e11)
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%e22 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %f12, <16 x i8> %k2)
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%f22 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %e12)
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%e23 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %f13, <16 x i8> %k2)
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%f23 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %e13)
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%b3 = getelementptr inbounds <16 x i8>, <16 x i8>* %b0, i64 3
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%k3 = load <16 x i8>, <16 x i8>* %b3
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%e30 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %f20, <16 x i8> %k3)
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%f30 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %e20)
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%e31 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %f21, <16 x i8> %k3)
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%f31 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %e21)
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%e32 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %f22, <16 x i8> %k3)
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%f32 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %e22)
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%e33 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %f23, <16 x i8> %k3)
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%f33 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %e23)
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%g0 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %f30, <16 x i8> %d)
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%h0 = xor <16 x i8> %g0, %e
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%g1 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %f31, <16 x i8> %d)
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%h1 = xor <16 x i8> %g1, %e
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%g2 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %f32, <16 x i8> %d)
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%h2 = xor <16 x i8> %g2, %e
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%g3 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %f33, <16 x i8> %d)
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%h3 = xor <16 x i8> %g3, %e
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store <16 x i8> %h0, <16 x i8>* %c0
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%c1 = getelementptr inbounds <16 x i8>, <16 x i8>* %c0, i64 1
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store <16 x i8> %h1, <16 x i8>* %c1
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%c2 = getelementptr inbounds <16 x i8>, <16 x i8>* %c0, i64 2
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store <16 x i8> %h2, <16 x i8>* %c2
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%c3 = getelementptr inbounds <16 x i8>, <16 x i8>* %c0, i64 3
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store <16 x i8> %h3, <16 x i8>* %c3
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ret void
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; CHECK-LABEL: aesea:
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; CHECK: aese.8 [[QA:q[0-9][0-9]?]], {{q[0-9][0-9]?}}
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; CHECK-NEXT: aesmc.8 {{q[0-9][0-9]?}}, [[QA]]
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; CHECK: aese.8 [[QB:q[0-9][0-9]?]], {{q[0-9][0-9]?}}
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; CHECK-NEXT: aesmc.8 {{q[0-9][0-9]?}}, [[QB]]
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; CHECK: aese.8 [[QC:q[0-9][0-9]?]], {{q[0-9][0-9]?}}
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; CHECK-NEXT: aesmc.8 {{q[0-9][0-9]?}}, [[QC]]
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; CHECK: aese.8 [[QD:q[0-9][0-9]?]], {{q[0-9][0-9]?}}
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; CHECK-NEXT: aesmc.8 {{q[0-9][0-9]?}}, [[QD]]
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; CHECK: aese.8 [[QE:q[0-9][0-9]?]], {{q[0-9][0-9]?}}
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; CHECK-NEXT: aesmc.8 {{q[0-9][0-9]?}}, [[QE]]
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; CHECK: aese.8 [[QF:q[0-9][0-9]?]], {{q[0-9][0-9]?}}
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; CHECK-NEXT: aesmc.8 {{q[0-9][0-9]?}}, [[QF]]
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; CHECK: aese.8 {{q[0-9][0-9]?}}, {{q[0-9][0-9]?}}
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; CHECK: aese.8 [[QG:q[0-9][0-9]?]], {{q[0-9][0-9]?}}
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; CHECK-NEXT: aesmc.8 {{q[0-9][0-9]?}}, [[QG]]
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; CHECK: aese.8 {{q[0-9][0-9]?}}, {{q[0-9][0-9]?}}
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; CHECK: aese.8 [[QH:q[0-9][0-9]?]], {{q[0-9][0-9]?}}
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; CHECK-NEXT: aesmc.8 {{q[0-9][0-9]?}}, [[QH]]
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}
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define void @aesda(<16 x i8>* %a0, <16 x i8>* %b0, <16 x i8>* %c0, <16 x i8> %d, <16 x i8> %e) {
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%d0 = load <16 x i8>, <16 x i8>* %a0
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%a1 = getelementptr inbounds <16 x i8>, <16 x i8>* %a0, i64 1
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%d1 = load <16 x i8>, <16 x i8>* %a1
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%a2 = getelementptr inbounds <16 x i8>, <16 x i8>* %a0, i64 2
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%d2 = load <16 x i8>, <16 x i8>* %a2
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%a3 = getelementptr inbounds <16 x i8>, <16 x i8>* %a0, i64 3
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%d3 = load <16 x i8>, <16 x i8>* %a3
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%k0 = load <16 x i8>, <16 x i8>* %b0
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%e00 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %d0, <16 x i8> %k0)
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%f00 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %e00)
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%e01 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %d1, <16 x i8> %k0)
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%f01 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %e01)
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%e02 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %d2, <16 x i8> %k0)
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%f02 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %e02)
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%e03 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %d3, <16 x i8> %k0)
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%f03 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %e03)
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%b1 = getelementptr inbounds <16 x i8>, <16 x i8>* %b0, i64 1
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%k1 = load <16 x i8>, <16 x i8>* %b1
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%e10 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %f00, <16 x i8> %k1)
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%f10 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %e00)
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%e11 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %f01, <16 x i8> %k1)
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%f11 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %e01)
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%e12 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %f02, <16 x i8> %k1)
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%f12 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %e02)
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%e13 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %f03, <16 x i8> %k1)
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%f13 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %e03)
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%b2 = getelementptr inbounds <16 x i8>, <16 x i8>* %b0, i64 2
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%k2 = load <16 x i8>, <16 x i8>* %b2
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%e20 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %f10, <16 x i8> %k2)
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%f20 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %e10)
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%e21 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %f11, <16 x i8> %k2)
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%f21 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %e11)
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%e22 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %f12, <16 x i8> %k2)
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%f22 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %e12)
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%e23 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %f13, <16 x i8> %k2)
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%f23 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %e13)
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%b3 = getelementptr inbounds <16 x i8>, <16 x i8>* %b0, i64 3
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%k3 = load <16 x i8>, <16 x i8>* %b3
|
||||
%e30 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %f20, <16 x i8> %k3)
|
||||
%f30 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %e20)
|
||||
%e31 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %f21, <16 x i8> %k3)
|
||||
%f31 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %e21)
|
||||
%e32 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %f22, <16 x i8> %k3)
|
||||
%f32 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %e22)
|
||||
%e33 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %f23, <16 x i8> %k3)
|
||||
%f33 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %e23)
|
||||
%g0 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %f30, <16 x i8> %d)
|
||||
%h0 = xor <16 x i8> %g0, %e
|
||||
%g1 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %f31, <16 x i8> %d)
|
||||
%h1 = xor <16 x i8> %g1, %e
|
||||
%g2 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %f32, <16 x i8> %d)
|
||||
%h2 = xor <16 x i8> %g2, %e
|
||||
%g3 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %f33, <16 x i8> %d)
|
||||
%h3 = xor <16 x i8> %g3, %e
|
||||
store <16 x i8> %h0, <16 x i8>* %c0
|
||||
%c1 = getelementptr inbounds <16 x i8>, <16 x i8>* %c0, i64 1
|
||||
store <16 x i8> %h1, <16 x i8>* %c1
|
||||
%c2 = getelementptr inbounds <16 x i8>, <16 x i8>* %c0, i64 2
|
||||
store <16 x i8> %h2, <16 x i8>* %c2
|
||||
%c3 = getelementptr inbounds <16 x i8>, <16 x i8>* %c0, i64 3
|
||||
store <16 x i8> %h3, <16 x i8>* %c3
|
||||
ret void
|
||||
|
||||
; CHECK-LABEL: aesda:
|
||||
; CHECK: aesd.8 [[QA:q[0-9][0-9]?]], {{q[0-9][0-9]?}}
|
||||
; CHECK-NEXT: aesimc.8 {{q[0-9][0-9]?}}, [[QA]]
|
||||
; CHECK: aesd.8 [[QB:q[0-9][0-9]?]], {{q[0-9][0-9]?}}
|
||||
; CHECK-NEXT: aesimc.8 {{q[0-9][0-9]?}}, [[QB]]
|
||||
; CHECK: aesd.8 [[QC:q[0-9][0-9]?]], {{q[0-9][0-9]?}}
|
||||
; CHECK-NEXT: aesimc.8 {{q[0-9][0-9]?}}, [[QC]]
|
||||
; CHECK: aesd.8 [[QD:q[0-9][0-9]?]], {{q[0-9][0-9]?}}
|
||||
; CHECK-NEXT: aesimc.8 {{q[0-9][0-9]?}}, [[QD]]
|
||||
; CHECK: aesd.8 [[QE:q[0-9][0-9]?]], {{q[0-9][0-9]?}}
|
||||
; CHECK-NEXT: aesimc.8 {{q[0-9][0-9]?}}, [[QE]]
|
||||
; CHECK: aesd.8 [[QF:q[0-9][0-9]?]], {{q[0-9][0-9]?}}
|
||||
; CHECK-NEXT: aesimc.8 {{q[0-9][0-9]?}}, [[QF]]
|
||||
; CHECK: aesd.8 {{q[0-9][0-9]?}}, {{q[0-9][0-9]?}}
|
||||
; CHECK: aesd.8 [[QG:q[0-9][0-9]?]], {{q[0-9][0-9]?}}
|
||||
; CHECK-NEXT: aesimc.8 {{q[0-9][0-9]?}}, [[QG]]
|
||||
; CHECK: aesd.8 {{q[0-9][0-9]?}}, {{q[0-9][0-9]?}}
|
||||
; CHECK: aesd.8 [[QH:q[0-9][0-9]?]], {{q[0-9][0-9]?}}
|
||||
; CHECK-NEXT: aesimc.8 {{q[0-9][0-9]?}}, [[QH]]
|
||||
}
|
||||
|
||||
define void @aes_load_store(<16 x i8> *%p1, <16 x i8> *%p2 , <16 x i8> *%p3) {
|
||||
entry:
|
||||
%x1 = alloca <16 x i8>, align 16
|
||||
%x2 = alloca <16 x i8>, align 16
|
||||
%x3 = alloca <16 x i8>, align 16
|
||||
%x4 = alloca <16 x i8>, align 16
|
||||
%x5 = alloca <16 x i8>, align 16
|
||||
%in1 = load <16 x i8>, <16 x i8>* %p1, align 16
|
||||
store <16 x i8> %in1, <16 x i8>* %x1, align 16
|
||||
%aese1 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %in1, <16 x i8> %in1) #2
|
||||
store <16 x i8> %aese1, <16 x i8>* %x2, align 16
|
||||
%in2 = load <16 x i8>, <16 x i8>* %p2, align 16
|
||||
%aesmc1= call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %aese1) #2
|
||||
store <16 x i8> %aesmc1, <16 x i8>* %x3, align 16
|
||||
%aese2 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %in1, <16 x i8> %in2) #2
|
||||
store <16 x i8> %aese2, <16 x i8>* %x4, align 16
|
||||
%aesmc2= call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %aese2) #2
|
||||
store <16 x i8> %aesmc2, <16 x i8>* %x5, align 16
|
||||
ret void
|
||||
|
||||
; CHECK-LABEL: aes_load_store:
|
||||
; CHECK: aese.8 [[QA:q[0-9][0-9]?]], {{q[0-9][0-9]?}}
|
||||
; CHECK-NEXT: aesmc.8 {{q[0-9][0-9]?}}, [[QA]]
|
||||
; CHECK: aese.8 [[QB:q[0-9][0-9]?]], {{q[0-9][0-9]?}}
|
||||
; CHECK-NEXT: aesmc.8 {{q[0-9][0-9]?}}, [[QB]]
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user