RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-01-31 20:51:52 +01:00
Code Issues Projects Releases Wiki Activity

Move three folds for FADD, FSUB and FMUL in the DAG combiner away from Unsafe to more aligned checks that reflect context

Browse Source 
Summary: Unsafe does not map well alone for each of these three cases as it is missing NoNan context when accessed directly with clang.  I have migrated the fold guards to reflect the expectations of handing nan and zero contexts directly (NoNan, NSZ) and some tests with it.  Unsafe does include NSZ, however there is already precedent for using the target option directly to reflect that context. 

Reviewers: spatel, wristow, hfinkel, craig.topper, arsenm

Reviewed By: arsenm

Subscribers: michele.scandale, wdng, javed.absar

Differential Revision: https://reviews.llvm.org/D64450

llvm-svn: 365679
This commit is contained in:
Michael Berg 2019-07-10 18:23:26 +00:00
parent 0c46c9cc2f
commit e6a923ea4b
4 changed files with 10 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -12030,8 +12030,8 @@ SDValue DAGCombiner::visitFADD(SDNode *N) {
// Selection pass has a hard time dealing with FP constants.
bool AllowNewConst = (Level < AfterLegalizeDAG);
// If 'unsafe math' or nnan is enabled, fold lots of things.
if ((Options.UnsafeFPMath || Flags.hasNoNaNs()) && AllowNewConst) {
// If nnan is enabled, fold lots of things.
if ((Options.NoNaNsFPMath || Flags.hasNoNaNs()) && AllowNewConst) {
// If allowed, fold (fadd (fneg x), x) -> 0.0
if (N0.getOpcode() == ISD::FNEG && N0.getOperand(0) == N1)
return DAG.getConstantFP(0.0, DL, VT);
@ -12171,7 +12171,7 @@ SDValue DAGCombiner::visitFSUB(SDNode *N) {
if (N0 == N1) {
// (fsub x, x) -> 0.0
if (Options.UnsafeFPMath || Flags.hasNoNaNs())
if (Options.NoNaNsFPMath || Flags.hasNoNaNs())
return DAG.getConstantFP(0.0f, DL, VT);
}
@ -12249,7 +12249,7 @@ SDValue DAGCombiner::visitFMUL(SDNode *N) {
if (SDValue NewSel = foldBinOpIntoSelect(N))
return NewSel;
if (Options.UnsafeFPMath ||
if ((Options.NoNaNsFPMath && Options.NoSignedZerosFPMath) ||
(Flags.hasNoNaNs() && Flags.hasNoSignedZeros())) {
// fold (fmul A, 0) -> 0
if (N1CFP && N1CFP->isZero())

2
test/CodeGen/ARM/unsafe-fsub.ll → test/CodeGen/ARM/nnan-fsub.ll
View File

@ -1,5 +1,5 @@
; RUN: llc -mcpu=cortex-a9 < %s | FileCheck -check-prefix=SAFE %s
; RUN: llc -mcpu=cortex-a9 -enable-unsafe-fp-math < %s | FileCheck -check-prefix=FAST %s
; RUN: llc -mcpu=cortex-a9 --enable-no-nans-fp-math < %s | FileCheck -check-prefix=FAST %s
target triple = "armv7-apple-ios"

8
test/CodeGen/X86/fmul-combines.ll
View File

@ -76,12 +76,12 @@ define <4 x float> @constant_fold_fmul_v4f32_undef(<4 x float> %x) {
ret <4 x float> %y
}
define <4 x float> @fmul0_v4f32(<4 x float> %x) #0 {
; CHECK-LABEL: fmul0_v4f32:
define <4 x float> @fmul0_v4f32_nsz_nnan(<4 x float> %x) #0 {
; CHECK-LABEL: fmul0_v4f32_nsz_nnan:
; CHECK: # %bb.0:
; CHECK-NEXT: xorps %xmm0, %xmm0
; CHECK-NEXT: retq
%y = fmul <4 x float> %x, <float 0.0, float 0.0, float 0.0, float 0.0>
%y = fmul nnan nsz <4 x float> %x, <float 0.0, float 0.0, float 0.0, float 0.0>
ret <4 x float> %y
}
@ -90,7 +90,7 @@ define <4 x float> @fmul0_v4f32_undef(<4 x float> %x) #0 {
; CHECK: # %bb.0:
; CHECK-NEXT: xorps %xmm0, %xmm0
; CHECK-NEXT: retq
%y = fmul <4 x float> %x, <float undef, float 0.0, float undef, float 0.0>
%y = fmul nnan nsz <4 x float> %x, <float undef, float 0.0, float undef, float 0.0>
ret <4 x float> %y
}

2
test/CodeGen/X86/fp-fast.ll
View File

@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=avx -enable-unsafe-fp-math < %s | FileCheck %s
; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=avx -enable-unsafe-fp-math --enable-no-nans-fp-math < %s | FileCheck %s
define float @test1(float %a) {
; CHECK-LABEL: test1: