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[DAGCombine] Combine pattern for REV16
This adds another pattern to the combiner for a case that we were not handling to generate the REV16 instruction for ARM/Thumb2 and a bswap+ror on X86. Differential Revision: https://reviews.llvm.org/D74032
This commit is contained in:
Sjoerd Meijer
parent
5038318cdb
commit
e6b39abdfb
@ -5648,6 +5648,48 @@ static bool isBSwapHWordPair(SDValue N, MutableArrayRef<SDNode *> Parts) {
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return false;
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}
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// Match this pattern:
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// (or (and (shl (A, 8)), 0xff00ff00), (and (srl (A, 8)), 0x00ff00ff))
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// And rewrite this to:
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// (rotr (bswap A), 16)
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static SDValue matchBSwapHWordOrAndAnd(const TargetLowering &TLI,
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SelectionDAG &DAG, SDNode *N, SDValue N0,
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SDValue N1, EVT VT, EVT ShiftAmountTy) {
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assert(N->getOpcode() == ISD::OR && VT == MVT::i32 &&
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"MatchBSwapHWordOrAndAnd: expecting i32");
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if (!TLI.isOperationLegalOrCustom(ISD::ROTR, VT))
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return SDValue();
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if (N0.getOpcode() != ISD::AND || N1.getOpcode() != ISD::AND)
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return SDValue();
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// TODO: this is too restrictive; lifting this restriction requires more tests
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if (!N0->hasOneUse() || !N1->hasOneUse())
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return SDValue();
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ConstantSDNode *Mask0 = isConstOrConstSplat(N0.getOperand(1));
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ConstantSDNode *Mask1 = isConstOrConstSplat(N1.getOperand(1));
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if (!Mask0 || !Mask1)
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return SDValue();
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if (Mask0->getAPIntValue() != 0xff00ff00 ||
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Mask1->getAPIntValue() != 0x00ff00ff)
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return SDValue();
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SDValue Shift0 = N0.getOperand(0);
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SDValue Shift1 = N1.getOperand(0);
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if (Shift0.getOpcode() != ISD::SHL || Shift1.getOpcode() != ISD::SRL)
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return SDValue();
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ConstantSDNode *ShiftAmt0 = isConstOrConstSplat(Shift0.getOperand(1));
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ConstantSDNode *ShiftAmt1 = isConstOrConstSplat(Shift1.getOperand(1));
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if (!ShiftAmt0 || !ShiftAmt1)
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return SDValue();
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if (ShiftAmt0->getAPIntValue() != 8 || ShiftAmt1->getAPIntValue() != 8)
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return SDValue();
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if (Shift0.getOperand(0) != Shift1.getOperand(0))
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return SDValue();
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SDLoc DL(N);
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SDValue BSwap = DAG.getNode(ISD::BSWAP, DL, VT, Shift0.getOperand(0));
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SDValue ShAmt = DAG.getConstant(16, DL, ShiftAmountTy);
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return DAG.getNode(ISD::ROTR, DL, VT, BSwap, ShAmt);
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}
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/// Match a 32-bit packed halfword bswap. That is
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/// ((x & 0x000000ff) << 8) |
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/// ((x & 0x0000ff00) >> 8) |
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@ -5664,6 +5706,16 @@ SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) {
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if (!TLI.isOperationLegalOrCustom(ISD::BSWAP, VT))
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return SDValue();
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if (SDValue BSwap = matchBSwapHWordOrAndAnd(TLI, DAG, N, N0, N1, VT,
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getShiftAmountTy(VT)))
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return BSwap;
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// Try again with commuted operands.
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if (SDValue BSwap = matchBSwapHWordOrAndAnd(TLI, DAG, N, N1, N0, VT,
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getShiftAmountTy(VT)))
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return BSwap;
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// Look for either
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// (or (bswaphpair), (bswaphpair))
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// (or (or (bswaphpair), (and)), (and))
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@ -1,11 +1,13 @@
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; XFAIL: *
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; fixme rev16 pattern is not matching
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; RUN: llc < %s -mtriple=thumb-- -mcpu=arm1156t2-s -mattr=+thumb2 | grep "rev16\W*r[0-9]*,\W*r[0-9]*" | count 1
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=thumbv7m-none-eabi -o - | FileCheck %s
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; 0xff00ff00 = 4278255360
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; 0x00ff00ff = 16711935
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define i32 @f1(i32 %a) {
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define i32 @rev16(i32 %a) {
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; CHECK-LABEL: rev16:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: rev16 r0, r0
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; CHECK-NEXT: bx lr
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%l8 = shl i32 %a, 8
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%r8 = lshr i32 %a, 8
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%mask_l8 = and i32 %l8, 4278255360
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@ -14,11 +16,142 @@ define i32 @f1(i32 %a) {
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ret i32 %tmp
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}
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define i32 @not_rev16(i32 %a) {
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; CHECK-LABEL: not_rev16:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: mov.w r1, #65280
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; CHECK-NEXT: and.w r1, r1, r0, lsr #8
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; CHECK-NEXT: and r0, r0, #65280
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; CHECK-NEXT: orr.w r0, r1, r0, lsl #8
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; CHECK-NEXT: bx lr
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%l8 = shl i32 %a, 8
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%r8 = lshr i32 %a, 8
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%mask_r8 = and i32 %r8, 4278255360
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%mask_l8 = and i32 %l8, 16711935
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%tmp = or i32 %mask_r8, %mask_l8
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ret i32 %tmp
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}
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define i32 @extra_maskop_uses2(i32 %a) {
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; CHECK-LABEL: extra_maskop_uses2:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: mov.w r1, #-16711936
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; CHECK-NEXT: mov.w r2, #16711935
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; CHECK-NEXT: and.w r1, r1, r0, lsl #8
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; CHECK-NEXT: and.w r0, r2, r0, lsr #8
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; CHECK-NEXT: adds r2, r0, r1
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; CHECK-NEXT: muls r0, r1, r0
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; CHECK-NEXT: muls r0, r2, r0
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; CHECK-NEXT: bx lr
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%l8 = shl i32 %a, 8
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%r8 = lshr i32 %a, 8
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%mask_l8 = and i32 %l8, 4278255360
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%mask_r8 = and i32 %r8, 16711935
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%or = or i32 %mask_r8, %mask_l8
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%mul = mul i32 %mask_r8, %mask_l8 ; another use of the mask ops
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%r = mul i32 %mul, %or ; and use that result
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ret i32 %r
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}
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define i32 @bswap_ror_commuted(i32 %a) {
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; CHECK-LABEL: bswap_ror_commuted:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: rev16 r0, r0
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; CHECK-NEXT: bx lr
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%l8 = shl i32 %a, 8
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%r8 = lshr i32 %a, 8
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%mask_l8 = and i32 %l8, 4278255360
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%mask_r8 = and i32 %r8, 16711935
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%tmp = or i32 %mask_r8, %mask_l8
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ret i32 %tmp
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}
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define i32 @different_shift_amount(i32 %a) {
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; CHECK-LABEL: different_shift_amount:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: mov.w r1, #16711935
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; CHECK-NEXT: movw r2, #65024
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; CHECK-NEXT: and.w r1, r1, r0, lsr #8
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; CHECK-NEXT: movt r2, #65280
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; CHECK-NEXT: and.w r0, r2, r0, lsl #9
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; CHECK-NEXT: add r0, r1
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; CHECK-NEXT: bx lr
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%l8 = shl i32 %a, 9
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%r8 = lshr i32 %a, 8
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%mask_l8 = and i32 %l8, 4278255360
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%mask_r8 = and i32 %r8, 16711935
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%tmp = or i32 %mask_l8, %mask_r8
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ret i32 %tmp
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}
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define i32 @different_constant(i32 %a) {
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; CHECK-LABEL: different_constant:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: mov.w r1, #16711935
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; CHECK-NEXT: and.w r0, r1, r0, lsr #8
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; CHECK-NEXT: bx lr
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%l8 = shl i32 %a, 8
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%r8 = lshr i32 %a, 8
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%mask_l8 = and i32 %l8, 42
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%mask_r8 = and i32 %r8, 16711935
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%tmp = or i32 %mask_l8, %mask_r8
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ret i32 %tmp
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}
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define i32 @different_op(i32 %a) {
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; CHECK-LABEL: different_op:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: mov.w r1, #16711935
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; CHECK-NEXT: movw r2, #256
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; CHECK-NEXT: and.w r1, r1, r0, lsr #8
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; CHECK-NEXT: movt r2, #255
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; CHECK-NEXT: add.w r0, r2, r0, lsl #8
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; CHECK-NEXT: orrs r0, r1
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; CHECK-NEXT: bx lr
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%l8 = shl i32 %a, 8
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%r8 = lshr i32 %a, 8
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%mask_l8 = sub i32 %l8, 4278255360
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%mask_r8 = and i32 %r8, 16711935
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%tmp = or i32 %mask_l8, %mask_r8
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ret i32 %tmp
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}
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define i32 @different_vars(i32 %a, i32 %b) {
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; CHECK-LABEL: different_vars:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: mov.w r2, #16711935
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; CHECK-NEXT: and.w r1, r2, r1, lsr #8
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; CHECK-NEXT: mov.w r2, #-16711936
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; CHECK-NEXT: and.w r0, r2, r0, lsl #8
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; CHECK-NEXT: add r0, r1
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; CHECK-NEXT: bx lr
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%l8 = shl i32 %a, 8
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%r8 = lshr i32 %b, 8
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%mask_l8 = and i32 %l8, 4278255360
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%mask_r8 = and i32 %r8, 16711935
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%tmp = or i32 %mask_l8, %mask_r8
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ret i32 %tmp
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}
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; FIXME: this rev16 pattern is not matching
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; 0xff000000 = 4278190080
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; 0x00ff0000 = 16711680
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; 0x0000ff00 = 65280
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; 0x000000ff = 255
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define i32 @f2(i32 %a) {
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; CHECK-LABEL: f2:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: mov.w r1, #16711680
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; CHECK-NEXT: and r2, r0, #16711680
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; CHECK-NEXT: and.w r1, r1, r0, lsr #8
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; CHECK-NEXT: orr.w r1, r1, r2, lsl #8
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; CHECK-NEXT: ubfx r2, r0, #8, #8
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; CHECK-NEXT: bfi r2, r0, #8, #8
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; CHECK-NEXT: adds r0, r2, r1
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; CHECK-NEXT: bx lr
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%l8 = shl i32 %a, 8
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%r8 = lshr i32 %a, 8
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%masklo_l8 = and i32 %l8, 65280
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@ -8,23 +8,15 @@ define i32 @rev16(i32 %a) {
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; X86-LABEL: rev16:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl %eax, %ecx
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; X86-NEXT: shll $8, %ecx
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; X86-NEXT: shrl $8, %eax
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; X86-NEXT: andl $-16711936, %ecx # imm = 0xFF00FF00
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; X86-NEXT: andl $16711935, %eax # imm = 0xFF00FF
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; X86-NEXT: orl %ecx, %eax
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; X86-NEXT: bswapl %eax
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; X86-NEXT: rorl $16, %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: rev16:
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; X64: # %bb.0:
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; X64-NEXT: # kill: def $edi killed $edi def $rdi
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: shll $8, %eax
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; X64-NEXT: shrl $8, %edi
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; X64-NEXT: andl $-16711936, %eax # imm = 0xFF00FF00
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; X64-NEXT: andl $16711935, %edi # imm = 0xFF00FF
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; X64-NEXT: addl %edi, %eax
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; X64-NEXT: bswapl %eax
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; X64-NEXT: rorl $16, %eax
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; X64-NEXT: retq
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%l8 = shl i32 %a, 8
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%r8 = lshr i32 %a, 8
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@ -104,23 +96,15 @@ define i32 @bswap_ror_commuted(i32 %a) {
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; X86-LABEL: bswap_ror_commuted:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl %eax, %ecx
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; X86-NEXT: shll $8, %ecx
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; X86-NEXT: shrl $8, %eax
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; X86-NEXT: andl $-16711936, %ecx # imm = 0xFF00FF00
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; X86-NEXT: andl $16711935, %eax # imm = 0xFF00FF
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; X86-NEXT: orl %ecx, %eax
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; X86-NEXT: bswapl %eax
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; X86-NEXT: rorl $16, %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: bswap_ror_commuted:
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; X64: # %bb.0:
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; X64-NEXT: # kill: def $edi killed $edi def $rdi
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: shll $8, %eax
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; X64-NEXT: shrl $8, %edi
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; X64-NEXT: andl $-16711936, %eax # imm = 0xFF00FF00
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; X64-NEXT: andl $16711935, %edi # imm = 0xFF00FF
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; X64-NEXT: addl %edi, %eax
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; X64-NEXT: bswapl %eax
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; X64-NEXT: rorl $16, %eax
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; X64-NEXT: retq
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%l8 = shl i32 %a, 8
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%r8 = lshr i32 %a, 8
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@ -241,8 +225,6 @@ define i32 @different_vars(i32 %a, i32 %b) {
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ret i32 %tmp
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}
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; TODO: another pattern that we are currently not matching
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;
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; 0xff000000 = 4278190080
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; 0x00ff0000 = 16711680
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; 0x0000ff00 = 65280
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