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[RISCV] Codegen support for RV32D floating point comparison operations
Also add double-prevoius-failure.ll which captures a test case that at one point triggered a compiler crash, while developing calling convention support for f64 on RV32D with soft-float ABI. llvm-svn: 329877
This commit is contained in:
Alex Bradbury
parent
258a56b182
commit
e6f9bc38ab
@ -108,13 +108,15 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::CTLZ, XLenVT, Expand);
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setOperationAction(ISD::CTPOP, XLenVT, Expand);
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ISD::CondCode FPCCToExtend[] = {
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ISD::SETOGT, ISD::SETOGE, ISD::SETONE, ISD::SETO, ISD::SETUEQ,
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ISD::SETUGT, ISD::SETUGE, ISD::SETULT, ISD::SETULE, ISD::SETUNE,
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ISD::SETGT, ISD::SETGE, ISD::SETNE};
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if (Subtarget.hasStdExtF()) {
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setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
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setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
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for (auto CC :
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{ISD::SETOGT, ISD::SETOGE, ISD::SETONE, ISD::SETO, ISD::SETUEQ,
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ISD::SETUGT, ISD::SETUGE, ISD::SETULT, ISD::SETULE, ISD::SETUNE,
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ISD::SETGT, ISD::SETGE, ISD::SETNE})
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for (auto CC : FPCCToExtend)
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setCondCodeAction(CC, MVT::f32, Expand);
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setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
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setOperationAction(ISD::SELECT, MVT::f32, Custom);
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@ -124,6 +126,11 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
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if (Subtarget.hasStdExtD()) {
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setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
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setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
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for (auto CC : FPCCToExtend)
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setCondCodeAction(CC, MVT::f64, Expand);
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setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
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setOperationAction(ISD::SELECT, MVT::f64, Custom);
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setOperationAction(ISD::BR_CC, MVT::f64, Expand);
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setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
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setTruncStoreAction(MVT::f64, MVT::f32, Expand);
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}
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@ -473,6 +480,7 @@ RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
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llvm_unreachable("Unexpected instr type to insert");
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case RISCV::Select_GPR_Using_CC_GPR:
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case RISCV::Select_FPR32_Using_CC_GPR:
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case RISCV::Select_FPR64_Using_CC_GPR:
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break;
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case RISCV::BuildPairF64Pseudo:
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return emitBuildPairF64Pseudo(MI, BB);
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@ -43,14 +43,18 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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return;
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}
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if (RISCV::FPR32RegClass.contains(DstReg, SrcReg)) {
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BuildMI(MBB, MBBI, DL, get(RISCV::FSGNJ_S), DstReg)
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.addReg(SrcReg, getKillRegState(KillSrc))
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.addReg(SrcReg, getKillRegState(KillSrc));
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return;
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}
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// FPR->FPR copies
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unsigned Opc;
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if (RISCV::FPR32RegClass.contains(DstReg, SrcReg))
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Opc = RISCV::FSGNJ_S;
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else if (RISCV::FPR64RegClass.contains(DstReg, SrcReg))
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Opc = RISCV::FSGNJ_D;
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else
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llvm_unreachable("Impossible reg-to-reg copy");
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llvm_unreachable("Impossible reg-to-reg copy");
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BuildMI(MBB, MBBI, DL, get(Opc), DstReg)
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.addReg(SrcReg, getKillRegState(KillSrc))
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.addReg(SrcReg, getKillRegState(KillSrc));
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}
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void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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@ -239,10 +239,24 @@ def : PatFpr64Fpr64<fmaxnum, FMAX_D>;
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/// Setcc
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def : PatFpr64Fpr64<seteq, FEQ_D>;
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def : PatFpr64Fpr64<setoeq, FEQ_D>;
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def : PatFpr64Fpr64<setlt, FLT_D>;
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def : PatFpr64Fpr64<setolt, FLT_D>;
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def : PatFpr64Fpr64<setle, FLE_D>;
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def : PatFpr64Fpr64<setole, FLE_D>;
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// Define pattern expansions for setcc operations which aren't directly
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// handled by a RISC-V instruction and aren't expanded in the SelectionDAG
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// Legalizer.
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def : Pat<(setuo FPR64:$rs1, FPR64:$rs2),
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(SLTIU (AND (FEQ_D FPR64:$rs1, FPR64:$rs1),
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(FEQ_D FPR64:$rs2, FPR64:$rs2)),
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1)>;
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def Select_FPR64_Using_CC_GPR : SelectCC_rrirr<FPR64, GPR>;
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/// Loads
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defm : LdPat<load, FLD>;
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534
test/CodeGen/RISCV/double-br-fcmp.ll
Normal file
534
test/CodeGen/RISCV/double-br-fcmp.ll
Normal file
@ -0,0 +1,534 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32IFD %s
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declare void @abort()
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declare void @exit(i32)
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define void @br_fcmp_false(double %a, double %b) nounwind {
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; RV32IFD-LABEL: br_fcmp_false:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw ra, 12(sp)
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; RV32IFD-NEXT: addi a0, zero, 1
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; RV32IFD-NEXT: bnez a0, .LBB0_2
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; RV32IFD-NEXT: # %bb.1: # %if.then
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; RV32IFD-NEXT: lw ra, 12(sp)
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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; RV32IFD-NEXT: .LBB0_2: # %if.else
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; RV32IFD-NEXT: lui a0, %hi(abort)
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; RV32IFD-NEXT: addi a0, a0, %lo(abort)
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; RV32IFD-NEXT: jalr a0
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%1 = fcmp false double %a, %b
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br i1 %1, label %if.then, label %if.else
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if.then:
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ret void
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if.else:
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tail call void @abort()
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unreachable
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}
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define void @br_fcmp_oeq(double %a, double %b) nounwind {
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; RV32IFD-LABEL: br_fcmp_oeq:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw ra, 12(sp)
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; RV32IFD-NEXT: sw a2, 0(sp)
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; RV32IFD-NEXT: sw a3, 4(sp)
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; RV32IFD-NEXT: fld ft0, 0(sp)
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; RV32IFD-NEXT: sw a0, 0(sp)
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; RV32IFD-NEXT: sw a1, 4(sp)
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; RV32IFD-NEXT: fld ft1, 0(sp)
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; RV32IFD-NEXT: feq.d a0, ft1, ft0
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; RV32IFD-NEXT: bnez a0, .LBB1_2
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; RV32IFD-NEXT: # %bb.1: # %if.else
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; RV32IFD-NEXT: lw ra, 12(sp)
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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; RV32IFD-NEXT: .LBB1_2: # %if.then
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; RV32IFD-NEXT: lui a0, %hi(abort)
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; RV32IFD-NEXT: addi a0, a0, %lo(abort)
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; RV32IFD-NEXT: jalr a0
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%1 = fcmp oeq double %a, %b
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br i1 %1, label %if.then, label %if.else
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if.else:
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ret void
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if.then:
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tail call void @abort()
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unreachable
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}
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; TODO: generated code quality for this is very poor due to
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; DAGCombiner::visitXOR converting the legal setoeq to setune, which requires
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; expansion.
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define void @br_fcmp_oeq_alt(double %a, double %b) nounwind {
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; RV32IFD-LABEL: br_fcmp_oeq_alt:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw ra, 12(sp)
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; RV32IFD-NEXT: sw a2, 0(sp)
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; RV32IFD-NEXT: sw a3, 4(sp)
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; RV32IFD-NEXT: fld ft0, 0(sp)
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; RV32IFD-NEXT: sw a0, 0(sp)
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; RV32IFD-NEXT: sw a1, 4(sp)
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; RV32IFD-NEXT: fld ft1, 0(sp)
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; RV32IFD-NEXT: feq.d a0, ft1, ft0
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; RV32IFD-NEXT: xori a0, a0, 1
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; RV32IFD-NEXT: beqz a0, .LBB2_2
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; RV32IFD-NEXT: # %bb.1: # %if.else
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; RV32IFD-NEXT: lw ra, 12(sp)
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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; RV32IFD-NEXT: .LBB2_2: # %if.then
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; RV32IFD-NEXT: lui a0, %hi(abort)
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; RV32IFD-NEXT: addi a0, a0, %lo(abort)
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; RV32IFD-NEXT: jalr a0
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%1 = fcmp oeq double %a, %b
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br i1 %1, label %if.then, label %if.else
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if.then:
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tail call void @abort()
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unreachable
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if.else:
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ret void
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}
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define void @br_fcmp_ogt(double %a, double %b) nounwind {
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; RV32IFD-LABEL: br_fcmp_ogt:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw ra, 12(sp)
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; RV32IFD-NEXT: sw a0, 0(sp)
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; RV32IFD-NEXT: sw a1, 4(sp)
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; RV32IFD-NEXT: fld ft0, 0(sp)
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; RV32IFD-NEXT: sw a2, 0(sp)
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; RV32IFD-NEXT: sw a3, 4(sp)
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; RV32IFD-NEXT: fld ft1, 0(sp)
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; RV32IFD-NEXT: flt.d a0, ft1, ft0
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; RV32IFD-NEXT: bnez a0, .LBB3_2
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; RV32IFD-NEXT: # %bb.1: # %if.else
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; RV32IFD-NEXT: lw ra, 12(sp)
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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; RV32IFD-NEXT: .LBB3_2: # %if.then
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; RV32IFD-NEXT: lui a0, %hi(abort)
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; RV32IFD-NEXT: addi a0, a0, %lo(abort)
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; RV32IFD-NEXT: jalr a0
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%1 = fcmp ogt double %a, %b
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br i1 %1, label %if.then, label %if.else
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if.else:
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ret void
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if.then:
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tail call void @abort()
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unreachable
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}
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define void @br_fcmp_oge(double %a, double %b) nounwind {
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; RV32IFD-LABEL: br_fcmp_oge:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw ra, 12(sp)
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; RV32IFD-NEXT: sw a0, 0(sp)
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; RV32IFD-NEXT: sw a1, 4(sp)
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; RV32IFD-NEXT: fld ft0, 0(sp)
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; RV32IFD-NEXT: sw a2, 0(sp)
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; RV32IFD-NEXT: sw a3, 4(sp)
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; RV32IFD-NEXT: fld ft1, 0(sp)
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; RV32IFD-NEXT: fle.d a0, ft1, ft0
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; RV32IFD-NEXT: bnez a0, .LBB4_2
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; RV32IFD-NEXT: # %bb.1: # %if.else
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; RV32IFD-NEXT: lw ra, 12(sp)
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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; RV32IFD-NEXT: .LBB4_2: # %if.then
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; RV32IFD-NEXT: lui a0, %hi(abort)
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; RV32IFD-NEXT: addi a0, a0, %lo(abort)
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; RV32IFD-NEXT: jalr a0
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%1 = fcmp oge double %a, %b
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br i1 %1, label %if.then, label %if.else
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if.else:
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ret void
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if.then:
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tail call void @abort()
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unreachable
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}
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define void @br_fcmp_olt(double %a, double %b) nounwind {
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; RV32IFD-LABEL: br_fcmp_olt:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw ra, 12(sp)
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; RV32IFD-NEXT: sw a2, 0(sp)
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; RV32IFD-NEXT: sw a3, 4(sp)
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; RV32IFD-NEXT: fld ft0, 0(sp)
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; RV32IFD-NEXT: sw a0, 0(sp)
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; RV32IFD-NEXT: sw a1, 4(sp)
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; RV32IFD-NEXT: fld ft1, 0(sp)
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; RV32IFD-NEXT: flt.d a0, ft1, ft0
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; RV32IFD-NEXT: bnez a0, .LBB5_2
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; RV32IFD-NEXT: # %bb.1: # %if.else
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; RV32IFD-NEXT: lw ra, 12(sp)
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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; RV32IFD-NEXT: .LBB5_2: # %if.then
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; RV32IFD-NEXT: lui a0, %hi(abort)
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; RV32IFD-NEXT: addi a0, a0, %lo(abort)
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; RV32IFD-NEXT: jalr a0
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%1 = fcmp olt double %a, %b
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br i1 %1, label %if.then, label %if.else
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if.else:
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ret void
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if.then:
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tail call void @abort()
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unreachable
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}
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define void @br_fcmp_ole(double %a, double %b) nounwind {
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; RV32IFD-LABEL: br_fcmp_ole:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw ra, 12(sp)
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; RV32IFD-NEXT: sw a2, 0(sp)
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; RV32IFD-NEXT: sw a3, 4(sp)
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; RV32IFD-NEXT: fld ft0, 0(sp)
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; RV32IFD-NEXT: sw a0, 0(sp)
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; RV32IFD-NEXT: sw a1, 4(sp)
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; RV32IFD-NEXT: fld ft1, 0(sp)
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; RV32IFD-NEXT: fle.d a0, ft1, ft0
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; RV32IFD-NEXT: bnez a0, .LBB6_2
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; RV32IFD-NEXT: # %bb.1: # %if.else
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; RV32IFD-NEXT: lw ra, 12(sp)
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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; RV32IFD-NEXT: .LBB6_2: # %if.then
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; RV32IFD-NEXT: lui a0, %hi(abort)
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; RV32IFD-NEXT: addi a0, a0, %lo(abort)
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; RV32IFD-NEXT: jalr a0
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%1 = fcmp ole double %a, %b
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br i1 %1, label %if.then, label %if.else
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if.else:
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ret void
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if.then:
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tail call void @abort()
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unreachable
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}
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; TODO: feq.s+sltiu+bne -> feq.s+beq
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define void @br_fcmp_one(double %a, double %b) nounwind {
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; RV32IFD-LABEL: br_fcmp_one:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw ra, 12(sp)
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; RV32IFD-NEXT: sw a0, 0(sp)
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; RV32IFD-NEXT: sw a1, 4(sp)
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; RV32IFD-NEXT: fld ft0, 0(sp)
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; RV32IFD-NEXT: sw a2, 0(sp)
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; RV32IFD-NEXT: sw a3, 4(sp)
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; RV32IFD-NEXT: fld ft1, 0(sp)
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; RV32IFD-NEXT: feq.d a0, ft1, ft1
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; RV32IFD-NEXT: feq.d a1, ft0, ft0
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; RV32IFD-NEXT: and a0, a1, a0
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; RV32IFD-NEXT: feq.d a1, ft0, ft1
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; RV32IFD-NEXT: not a1, a1
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; RV32IFD-NEXT: seqz a0, a0
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; RV32IFD-NEXT: xori a0, a0, 1
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; RV32IFD-NEXT: and a0, a1, a0
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; RV32IFD-NEXT: bnez a0, .LBB7_2
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; RV32IFD-NEXT: # %bb.1: # %if.else
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; RV32IFD-NEXT: lw ra, 12(sp)
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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; RV32IFD-NEXT: .LBB7_2: # %if.then
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; RV32IFD-NEXT: lui a0, %hi(abort)
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; RV32IFD-NEXT: addi a0, a0, %lo(abort)
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; RV32IFD-NEXT: jalr a0
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%1 = fcmp one double %a, %b
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br i1 %1, label %if.then, label %if.else
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if.else:
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ret void
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if.then:
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tail call void @abort()
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unreachable
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}
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define void @br_fcmp_ord(double %a, double %b) nounwind {
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; RV32IFD-LABEL: br_fcmp_ord:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw ra, 12(sp)
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; RV32IFD-NEXT: sw a0, 0(sp)
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; RV32IFD-NEXT: sw a1, 4(sp)
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; RV32IFD-NEXT: fld ft0, 0(sp)
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; RV32IFD-NEXT: sw a2, 0(sp)
|
||||
; RV32IFD-NEXT: sw a3, 4(sp)
|
||||
; RV32IFD-NEXT: fld ft1, 0(sp)
|
||||
; RV32IFD-NEXT: feq.d a0, ft1, ft1
|
||||
; RV32IFD-NEXT: feq.d a1, ft0, ft0
|
||||
; RV32IFD-NEXT: and a0, a1, a0
|
||||
; RV32IFD-NEXT: seqz a0, a0
|
||||
; RV32IFD-NEXT: xori a0, a0, 1
|
||||
; RV32IFD-NEXT: bnez a0, .LBB8_2
|
||||
; RV32IFD-NEXT: # %bb.1: # %if.else
|
||||
; RV32IFD-NEXT: lw ra, 12(sp)
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
; RV32IFD-NEXT: .LBB8_2: # %if.then
|
||||
; RV32IFD-NEXT: lui a0, %hi(abort)
|
||||
; RV32IFD-NEXT: addi a0, a0, %lo(abort)
|
||||
; RV32IFD-NEXT: jalr a0
|
||||
%1 = fcmp ord double %a, %b
|
||||
br i1 %1, label %if.then, label %if.else
|
||||
if.else:
|
||||
ret void
|
||||
if.then:
|
||||
tail call void @abort()
|
||||
unreachable
|
||||
}
|
||||
|
||||
define void @br_fcmp_ueq(double %a, double %b) nounwind {
|
||||
; RV32IFD-LABEL: br_fcmp_ueq:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: sw ra, 12(sp)
|
||||
; RV32IFD-NEXT: sw a2, 0(sp)
|
||||
; RV32IFD-NEXT: sw a3, 4(sp)
|
||||
; RV32IFD-NEXT: fld ft0, 0(sp)
|
||||
; RV32IFD-NEXT: sw a0, 0(sp)
|
||||
; RV32IFD-NEXT: sw a1, 4(sp)
|
||||
; RV32IFD-NEXT: fld ft1, 0(sp)
|
||||
; RV32IFD-NEXT: feq.d a0, ft1, ft0
|
||||
; RV32IFD-NEXT: feq.d a1, ft0, ft0
|
||||
; RV32IFD-NEXT: feq.d a2, ft1, ft1
|
||||
; RV32IFD-NEXT: and a1, a2, a1
|
||||
; RV32IFD-NEXT: seqz a1, a1
|
||||
; RV32IFD-NEXT: or a0, a0, a1
|
||||
; RV32IFD-NEXT: bnez a0, .LBB9_2
|
||||
; RV32IFD-NEXT: # %bb.1: # %if.else
|
||||
; RV32IFD-NEXT: lw ra, 12(sp)
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
; RV32IFD-NEXT: .LBB9_2: # %if.then
|
||||
; RV32IFD-NEXT: lui a0, %hi(abort)
|
||||
; RV32IFD-NEXT: addi a0, a0, %lo(abort)
|
||||
; RV32IFD-NEXT: jalr a0
|
||||
%1 = fcmp ueq double %a, %b
|
||||
br i1 %1, label %if.then, label %if.else
|
||||
if.else:
|
||||
ret void
|
||||
if.then:
|
||||
tail call void @abort()
|
||||
unreachable
|
||||
}
|
||||
|
||||
define void @br_fcmp_ugt(double %a, double %b) nounwind {
|
||||
; RV32IFD-LABEL: br_fcmp_ugt:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: sw ra, 12(sp)
|
||||
; RV32IFD-NEXT: sw a2, 0(sp)
|
||||
; RV32IFD-NEXT: sw a3, 4(sp)
|
||||
; RV32IFD-NEXT: fld ft0, 0(sp)
|
||||
; RV32IFD-NEXT: sw a0, 0(sp)
|
||||
; RV32IFD-NEXT: sw a1, 4(sp)
|
||||
; RV32IFD-NEXT: fld ft1, 0(sp)
|
||||
; RV32IFD-NEXT: fle.d a0, ft1, ft0
|
||||
; RV32IFD-NEXT: xori a0, a0, 1
|
||||
; RV32IFD-NEXT: bnez a0, .LBB10_2
|
||||
; RV32IFD-NEXT: # %bb.1: # %if.else
|
||||
; RV32IFD-NEXT: lw ra, 12(sp)
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
; RV32IFD-NEXT: .LBB10_2: # %if.then
|
||||
; RV32IFD-NEXT: lui a0, %hi(abort)
|
||||
; RV32IFD-NEXT: addi a0, a0, %lo(abort)
|
||||
; RV32IFD-NEXT: jalr a0
|
||||
%1 = fcmp ugt double %a, %b
|
||||
br i1 %1, label %if.then, label %if.else
|
||||
if.else:
|
||||
ret void
|
||||
if.then:
|
||||
tail call void @abort()
|
||||
unreachable
|
||||
}
|
||||
|
||||
define void @br_fcmp_uge(double %a, double %b) nounwind {
|
||||
; RV32IFD-LABEL: br_fcmp_uge:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: sw ra, 12(sp)
|
||||
; RV32IFD-NEXT: sw a2, 0(sp)
|
||||
; RV32IFD-NEXT: sw a3, 4(sp)
|
||||
; RV32IFD-NEXT: fld ft0, 0(sp)
|
||||
; RV32IFD-NEXT: sw a0, 0(sp)
|
||||
; RV32IFD-NEXT: sw a1, 4(sp)
|
||||
; RV32IFD-NEXT: fld ft1, 0(sp)
|
||||
; RV32IFD-NEXT: flt.d a0, ft1, ft0
|
||||
; RV32IFD-NEXT: xori a0, a0, 1
|
||||
; RV32IFD-NEXT: bnez a0, .LBB11_2
|
||||
; RV32IFD-NEXT: # %bb.1: # %if.else
|
||||
; RV32IFD-NEXT: lw ra, 12(sp)
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
; RV32IFD-NEXT: .LBB11_2: # %if.then
|
||||
; RV32IFD-NEXT: lui a0, %hi(abort)
|
||||
; RV32IFD-NEXT: addi a0, a0, %lo(abort)
|
||||
; RV32IFD-NEXT: jalr a0
|
||||
%1 = fcmp uge double %a, %b
|
||||
br i1 %1, label %if.then, label %if.else
|
||||
if.else:
|
||||
ret void
|
||||
if.then:
|
||||
tail call void @abort()
|
||||
unreachable
|
||||
}
|
||||
|
||||
define void @br_fcmp_ult(double %a, double %b) nounwind {
|
||||
; RV32IFD-LABEL: br_fcmp_ult:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: sw ra, 12(sp)
|
||||
; RV32IFD-NEXT: sw a0, 0(sp)
|
||||
; RV32IFD-NEXT: sw a1, 4(sp)
|
||||
; RV32IFD-NEXT: fld ft0, 0(sp)
|
||||
; RV32IFD-NEXT: sw a2, 0(sp)
|
||||
; RV32IFD-NEXT: sw a3, 4(sp)
|
||||
; RV32IFD-NEXT: fld ft1, 0(sp)
|
||||
; RV32IFD-NEXT: fle.d a0, ft1, ft0
|
||||
; RV32IFD-NEXT: xori a0, a0, 1
|
||||
; RV32IFD-NEXT: bnez a0, .LBB12_2
|
||||
; RV32IFD-NEXT: # %bb.1: # %if.else
|
||||
; RV32IFD-NEXT: lw ra, 12(sp)
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
; RV32IFD-NEXT: .LBB12_2: # %if.then
|
||||
; RV32IFD-NEXT: lui a0, %hi(abort)
|
||||
; RV32IFD-NEXT: addi a0, a0, %lo(abort)
|
||||
; RV32IFD-NEXT: jalr a0
|
||||
%1 = fcmp ult double %a, %b
|
||||
br i1 %1, label %if.then, label %if.else
|
||||
if.else:
|
||||
ret void
|
||||
if.then:
|
||||
tail call void @abort()
|
||||
unreachable
|
||||
}
|
||||
|
||||
define void @br_fcmp_ule(double %a, double %b) nounwind {
|
||||
; RV32IFD-LABEL: br_fcmp_ule:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: sw ra, 12(sp)
|
||||
; RV32IFD-NEXT: sw a0, 0(sp)
|
||||
; RV32IFD-NEXT: sw a1, 4(sp)
|
||||
; RV32IFD-NEXT: fld ft0, 0(sp)
|
||||
; RV32IFD-NEXT: sw a2, 0(sp)
|
||||
; RV32IFD-NEXT: sw a3, 4(sp)
|
||||
; RV32IFD-NEXT: fld ft1, 0(sp)
|
||||
; RV32IFD-NEXT: flt.d a0, ft1, ft0
|
||||
; RV32IFD-NEXT: xori a0, a0, 1
|
||||
; RV32IFD-NEXT: bnez a0, .LBB13_2
|
||||
; RV32IFD-NEXT: # %bb.1: # %if.else
|
||||
; RV32IFD-NEXT: lw ra, 12(sp)
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
; RV32IFD-NEXT: .LBB13_2: # %if.then
|
||||
; RV32IFD-NEXT: lui a0, %hi(abort)
|
||||
; RV32IFD-NEXT: addi a0, a0, %lo(abort)
|
||||
; RV32IFD-NEXT: jalr a0
|
||||
%1 = fcmp ule double %a, %b
|
||||
br i1 %1, label %if.then, label %if.else
|
||||
if.else:
|
||||
ret void
|
||||
if.then:
|
||||
tail call void @abort()
|
||||
unreachable
|
||||
}
|
||||
|
||||
define void @br_fcmp_une(double %a, double %b) nounwind {
|
||||
; RV32IFD-LABEL: br_fcmp_une:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: sw ra, 12(sp)
|
||||
; RV32IFD-NEXT: sw a2, 0(sp)
|
||||
; RV32IFD-NEXT: sw a3, 4(sp)
|
||||
; RV32IFD-NEXT: fld ft0, 0(sp)
|
||||
; RV32IFD-NEXT: sw a0, 0(sp)
|
||||
; RV32IFD-NEXT: sw a1, 4(sp)
|
||||
; RV32IFD-NEXT: fld ft1, 0(sp)
|
||||
; RV32IFD-NEXT: feq.d a0, ft1, ft0
|
||||
; RV32IFD-NEXT: xori a0, a0, 1
|
||||
; RV32IFD-NEXT: bnez a0, .LBB14_2
|
||||
; RV32IFD-NEXT: # %bb.1: # %if.else
|
||||
; RV32IFD-NEXT: lw ra, 12(sp)
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
; RV32IFD-NEXT: .LBB14_2: # %if.then
|
||||
; RV32IFD-NEXT: lui a0, %hi(abort)
|
||||
; RV32IFD-NEXT: addi a0, a0, %lo(abort)
|
||||
; RV32IFD-NEXT: jalr a0
|
||||
%1 = fcmp une double %a, %b
|
||||
br i1 %1, label %if.then, label %if.else
|
||||
if.else:
|
||||
ret void
|
||||
if.then:
|
||||
tail call void @abort()
|
||||
unreachable
|
||||
}
|
||||
|
||||
define void @br_fcmp_uno(double %a, double %b) nounwind {
|
||||
; TODO: sltiu+bne -> beq
|
||||
; RV32IFD-LABEL: br_fcmp_uno:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: sw ra, 12(sp)
|
||||
; RV32IFD-NEXT: sw a0, 0(sp)
|
||||
; RV32IFD-NEXT: sw a1, 4(sp)
|
||||
; RV32IFD-NEXT: fld ft0, 0(sp)
|
||||
; RV32IFD-NEXT: sw a2, 0(sp)
|
||||
; RV32IFD-NEXT: sw a3, 4(sp)
|
||||
; RV32IFD-NEXT: fld ft1, 0(sp)
|
||||
; RV32IFD-NEXT: feq.d a0, ft1, ft1
|
||||
; RV32IFD-NEXT: feq.d a1, ft0, ft0
|
||||
; RV32IFD-NEXT: and a0, a1, a0
|
||||
; RV32IFD-NEXT: seqz a0, a0
|
||||
; RV32IFD-NEXT: bnez a0, .LBB15_2
|
||||
; RV32IFD-NEXT: # %bb.1: # %if.else
|
||||
; RV32IFD-NEXT: lw ra, 12(sp)
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
; RV32IFD-NEXT: .LBB15_2: # %if.then
|
||||
; RV32IFD-NEXT: lui a0, %hi(abort)
|
||||
; RV32IFD-NEXT: addi a0, a0, %lo(abort)
|
||||
; RV32IFD-NEXT: jalr a0
|
||||
%1 = fcmp uno double %a, %b
|
||||
br i1 %1, label %if.then, label %if.else
|
||||
if.else:
|
||||
ret void
|
||||
if.then:
|
||||
tail call void @abort()
|
||||
unreachable
|
||||
}
|
||||
|
||||
define void @br_fcmp_true(double %a, double %b) nounwind {
|
||||
; RV32IFD-LABEL: br_fcmp_true:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: sw ra, 12(sp)
|
||||
; RV32IFD-NEXT: addi a0, zero, 1
|
||||
; RV32IFD-NEXT: bnez a0, .LBB16_2
|
||||
; RV32IFD-NEXT: # %bb.1: # %if.else
|
||||
; RV32IFD-NEXT: lw ra, 12(sp)
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
; RV32IFD-NEXT: .LBB16_2: # %if.then
|
||||
; RV32IFD-NEXT: lui a0, %hi(abort)
|
||||
; RV32IFD-NEXT: addi a0, a0, %lo(abort)
|
||||
; RV32IFD-NEXT: jalr a0
|
||||
%1 = fcmp true double %a, %b
|
||||
br i1 %1, label %if.then, label %if.else
|
||||
if.else:
|
||||
ret void
|
||||
if.then:
|
||||
tail call void @abort()
|
||||
unreachable
|
||||
}
|
||||
299
test/CodeGen/RISCV/double-fcmp.ll
Normal file
299
test/CodeGen/RISCV/double-fcmp.ll
Normal file
@ -0,0 +1,299 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
|
||||
; RUN: | FileCheck -check-prefix=RV32IFD %s
|
||||
|
||||
define i32 @fcmp_false(double %a, double %b) nounwind {
|
||||
; RV32IFD-LABEL: fcmp_false:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: mv a0, zero
|
||||
; RV32IFD-NEXT: ret
|
||||
%1 = fcmp false double %a, %b
|
||||
%2 = zext i1 %1 to i32
|
||||
ret i32 %2
|
||||
}
|
||||
|
||||
define i32 @fcmp_oeq(double %a, double %b) nounwind {
|
||||
; RV32IFD-LABEL: fcmp_oeq:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: sw a2, 8(sp)
|
||||
; RV32IFD-NEXT: sw a3, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a1, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft1, 8(sp)
|
||||
; RV32IFD-NEXT: feq.d a0, ft1, ft0
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
%1 = fcmp oeq double %a, %b
|
||||
%2 = zext i1 %1 to i32
|
||||
ret i32 %2
|
||||
}
|
||||
|
||||
define i32 @fcmp_ogt(double %a, double %b) nounwind {
|
||||
; RV32IFD-LABEL: fcmp_ogt:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: sw a0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a1, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a2, 8(sp)
|
||||
; RV32IFD-NEXT: sw a3, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft1, 8(sp)
|
||||
; RV32IFD-NEXT: flt.d a0, ft1, ft0
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
%1 = fcmp ogt double %a, %b
|
||||
%2 = zext i1 %1 to i32
|
||||
ret i32 %2
|
||||
}
|
||||
|
||||
define i32 @fcmp_oge(double %a, double %b) nounwind {
|
||||
; RV32IFD-LABEL: fcmp_oge:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: sw a0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a1, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a2, 8(sp)
|
||||
; RV32IFD-NEXT: sw a3, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft1, 8(sp)
|
||||
; RV32IFD-NEXT: fle.d a0, ft1, ft0
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
%1 = fcmp oge double %a, %b
|
||||
%2 = zext i1 %1 to i32
|
||||
ret i32 %2
|
||||
}
|
||||
|
||||
define i32 @fcmp_olt(double %a, double %b) nounwind {
|
||||
; RV32IFD-LABEL: fcmp_olt:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: sw a2, 8(sp)
|
||||
; RV32IFD-NEXT: sw a3, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a1, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft1, 8(sp)
|
||||
; RV32IFD-NEXT: flt.d a0, ft1, ft0
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
%1 = fcmp olt double %a, %b
|
||||
%2 = zext i1 %1 to i32
|
||||
ret i32 %2
|
||||
}
|
||||
|
||||
define i32 @fcmp_ole(double %a, double %b) nounwind {
|
||||
; RV32IFD-LABEL: fcmp_ole:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: sw a2, 8(sp)
|
||||
; RV32IFD-NEXT: sw a3, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a1, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft1, 8(sp)
|
||||
; RV32IFD-NEXT: fle.d a0, ft1, ft0
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
%1 = fcmp ole double %a, %b
|
||||
%2 = zext i1 %1 to i32
|
||||
ret i32 %2
|
||||
}
|
||||
|
||||
define i32 @fcmp_one(double %a, double %b) nounwind {
|
||||
; RV32IFD-LABEL: fcmp_one:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: sw a0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a1, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a2, 8(sp)
|
||||
; RV32IFD-NEXT: sw a3, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft1, 8(sp)
|
||||
; RV32IFD-NEXT: feq.d a0, ft1, ft1
|
||||
; RV32IFD-NEXT: feq.d a1, ft0, ft0
|
||||
; RV32IFD-NEXT: and a0, a1, a0
|
||||
; RV32IFD-NEXT: feq.d a1, ft0, ft1
|
||||
; RV32IFD-NEXT: not a1, a1
|
||||
; RV32IFD-NEXT: seqz a0, a0
|
||||
; RV32IFD-NEXT: xori a0, a0, 1
|
||||
; RV32IFD-NEXT: and a0, a1, a0
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
%1 = fcmp one double %a, %b
|
||||
%2 = zext i1 %1 to i32
|
||||
ret i32 %2
|
||||
}
|
||||
|
||||
define i32 @fcmp_ord(double %a, double %b) nounwind {
|
||||
; RV32IFD-LABEL: fcmp_ord:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: sw a0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a1, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a2, 8(sp)
|
||||
; RV32IFD-NEXT: sw a3, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft1, 8(sp)
|
||||
; RV32IFD-NEXT: feq.d a0, ft1, ft1
|
||||
; RV32IFD-NEXT: feq.d a1, ft0, ft0
|
||||
; RV32IFD-NEXT: and a0, a1, a0
|
||||
; RV32IFD-NEXT: seqz a0, a0
|
||||
; RV32IFD-NEXT: xori a0, a0, 1
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
%1 = fcmp ord double %a, %b
|
||||
%2 = zext i1 %1 to i32
|
||||
ret i32 %2
|
||||
}
|
||||
|
||||
define i32 @fcmp_ueq(double %a, double %b) nounwind {
|
||||
; RV32IFD-LABEL: fcmp_ueq:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: sw a2, 8(sp)
|
||||
; RV32IFD-NEXT: sw a3, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a1, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft1, 8(sp)
|
||||
; RV32IFD-NEXT: feq.d a0, ft1, ft0
|
||||
; RV32IFD-NEXT: feq.d a1, ft0, ft0
|
||||
; RV32IFD-NEXT: feq.d a2, ft1, ft1
|
||||
; RV32IFD-NEXT: and a1, a2, a1
|
||||
; RV32IFD-NEXT: seqz a1, a1
|
||||
; RV32IFD-NEXT: or a0, a0, a1
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
%1 = fcmp ueq double %a, %b
|
||||
%2 = zext i1 %1 to i32
|
||||
ret i32 %2
|
||||
}
|
||||
|
||||
define i32 @fcmp_ugt(double %a, double %b) nounwind {
|
||||
; RV32IFD-LABEL: fcmp_ugt:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: sw a2, 8(sp)
|
||||
; RV32IFD-NEXT: sw a3, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a1, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft1, 8(sp)
|
||||
; RV32IFD-NEXT: fle.d a0, ft1, ft0
|
||||
; RV32IFD-NEXT: xori a0, a0, 1
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
%1 = fcmp ugt double %a, %b
|
||||
%2 = zext i1 %1 to i32
|
||||
ret i32 %2
|
||||
}
|
||||
|
||||
define i32 @fcmp_uge(double %a, double %b) nounwind {
|
||||
; RV32IFD-LABEL: fcmp_uge:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: sw a2, 8(sp)
|
||||
; RV32IFD-NEXT: sw a3, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a1, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft1, 8(sp)
|
||||
; RV32IFD-NEXT: flt.d a0, ft1, ft0
|
||||
; RV32IFD-NEXT: xori a0, a0, 1
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
%1 = fcmp uge double %a, %b
|
||||
%2 = zext i1 %1 to i32
|
||||
ret i32 %2
|
||||
}
|
||||
|
||||
define i32 @fcmp_ult(double %a, double %b) nounwind {
|
||||
; RV32IFD-LABEL: fcmp_ult:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: sw a0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a1, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a2, 8(sp)
|
||||
; RV32IFD-NEXT: sw a3, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft1, 8(sp)
|
||||
; RV32IFD-NEXT: fle.d a0, ft1, ft0
|
||||
; RV32IFD-NEXT: xori a0, a0, 1
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
%1 = fcmp ult double %a, %b
|
||||
%2 = zext i1 %1 to i32
|
||||
ret i32 %2
|
||||
}
|
||||
|
||||
define i32 @fcmp_ule(double %a, double %b) nounwind {
|
||||
; RV32IFD-LABEL: fcmp_ule:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: sw a0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a1, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a2, 8(sp)
|
||||
; RV32IFD-NEXT: sw a3, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft1, 8(sp)
|
||||
; RV32IFD-NEXT: flt.d a0, ft1, ft0
|
||||
; RV32IFD-NEXT: xori a0, a0, 1
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
%1 = fcmp ule double %a, %b
|
||||
%2 = zext i1 %1 to i32
|
||||
ret i32 %2
|
||||
}
|
||||
|
||||
define i32 @fcmp_une(double %a, double %b) nounwind {
|
||||
; RV32IFD-LABEL: fcmp_une:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: sw a2, 8(sp)
|
||||
; RV32IFD-NEXT: sw a3, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a1, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft1, 8(sp)
|
||||
; RV32IFD-NEXT: feq.d a0, ft1, ft0
|
||||
; RV32IFD-NEXT: xori a0, a0, 1
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
%1 = fcmp une double %a, %b
|
||||
%2 = zext i1 %1 to i32
|
||||
ret i32 %2
|
||||
}
|
||||
|
||||
define i32 @fcmp_uno(double %a, double %b) nounwind {
|
||||
; RV32IFD-LABEL: fcmp_uno:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: sw a0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a1, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a2, 8(sp)
|
||||
; RV32IFD-NEXT: sw a3, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft1, 8(sp)
|
||||
; RV32IFD-NEXT: feq.d a0, ft1, ft1
|
||||
; RV32IFD-NEXT: feq.d a1, ft0, ft0
|
||||
; RV32IFD-NEXT: and a0, a1, a0
|
||||
; RV32IFD-NEXT: seqz a0, a0
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
%1 = fcmp uno double %a, %b
|
||||
%2 = zext i1 %1 to i32
|
||||
ret i32 %2
|
||||
}
|
||||
|
||||
define i32 @fcmp_true(double %a, double %b) nounwind {
|
||||
; RV32IFD-LABEL: fcmp_true:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi a0, zero, 1
|
||||
; RV32IFD-NEXT: ret
|
||||
%1 = fcmp true double %a, %b
|
||||
%2 = zext i1 %1 to i32
|
||||
ret i32 %2
|
||||
}
|
||||
71
test/CodeGen/RISCV/double-previous-failure.ll
Normal file
71
test/CodeGen/RISCV/double-previous-failure.ll
Normal file
@ -0,0 +1,71 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
|
||||
; RUN: | FileCheck -check-prefix=RV32IFD %s
|
||||
|
||||
define double @test(double %a) nounwind {
|
||||
; RV32IFD-LABEL: test:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: ret
|
||||
ret double %a
|
||||
}
|
||||
|
||||
; This previously failed complaining of multiple vreg defs due to an ABI
|
||||
; lowering issue.
|
||||
|
||||
define i32 @main() nounwind {
|
||||
; RV32IFD-LABEL: main:
|
||||
; RV32IFD: # %bb.0: # %entry
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: sw ra, 12(sp)
|
||||
; RV32IFD-NEXT: lui a0, %hi(test)
|
||||
; RV32IFD-NEXT: addi a2, a0, %lo(test)
|
||||
; RV32IFD-NEXT: lui a0, %hi(.LCPI1_0)
|
||||
; RV32IFD-NEXT: addi a0, a0, %lo(.LCPI1_0)
|
||||
; RV32IFD-NEXT: fld ft0, 0(a0)
|
||||
; RV32IFD-NEXT: fsd ft0, 0(sp)
|
||||
; RV32IFD-NEXT: lw a0, 0(sp)
|
||||
; RV32IFD-NEXT: lw a1, 4(sp)
|
||||
; RV32IFD-NEXT: jalr a2
|
||||
; RV32IFD-NEXT: sw a0, 0(sp)
|
||||
; RV32IFD-NEXT: sw a1, 4(sp)
|
||||
; RV32IFD-NEXT: fld ft0, 0(sp)
|
||||
; RV32IFD-NEXT: lui a0, %hi(.LCPI1_1)
|
||||
; RV32IFD-NEXT: addi a0, a0, %lo(.LCPI1_1)
|
||||
; RV32IFD-NEXT: fld ft1, 0(a0)
|
||||
; RV32IFD-NEXT: flt.d a0, ft0, ft1
|
||||
; RV32IFD-NEXT: bnez a0, .LBB1_3
|
||||
; RV32IFD-NEXT: # %bb.1: # %entry
|
||||
; RV32IFD-NEXT: lui a0, %hi(.LCPI1_2)
|
||||
; RV32IFD-NEXT: addi a0, a0, %lo(.LCPI1_2)
|
||||
; RV32IFD-NEXT: fld ft1, 0(a0)
|
||||
; RV32IFD-NEXT: flt.d a0, ft1, ft0
|
||||
; RV32IFD-NEXT: xori a0, a0, 1
|
||||
; RV32IFD-NEXT: beqz a0, .LBB1_3
|
||||
; RV32IFD-NEXT: # %bb.2: # %if.end
|
||||
; RV32IFD-NEXT: lui a0, %hi(exit)
|
||||
; RV32IFD-NEXT: addi a1, a0, %lo(exit)
|
||||
; RV32IFD-NEXT: mv a0, zero
|
||||
; RV32IFD-NEXT: jalr a1
|
||||
; RV32IFD-NEXT: .LBB1_3: # %if.then
|
||||
; RV32IFD-NEXT: lui a0, %hi(abort)
|
||||
; RV32IFD-NEXT: addi a0, a0, %lo(abort)
|
||||
; RV32IFD-NEXT: jalr a0
|
||||
entry:
|
||||
%call = call double @test(double 2.000000e+00)
|
||||
%cmp = fcmp olt double %call, 2.400000e-01
|
||||
%cmp2 = fcmp ogt double %call, 2.600000e-01
|
||||
%or.cond = or i1 %cmp, %cmp2
|
||||
br i1 %or.cond, label %if.then, label %if.end
|
||||
|
||||
if.then:
|
||||
call void @abort()
|
||||
unreachable
|
||||
|
||||
if.end:
|
||||
call void @exit(i32 0)
|
||||
unreachable
|
||||
}
|
||||
|
||||
declare void @abort()
|
||||
|
||||
declare void @exit(i32)
|
||||
423
test/CodeGen/RISCV/double-select-fcmp.ll
Normal file
423
test/CodeGen/RISCV/double-select-fcmp.ll
Normal file
@ -0,0 +1,423 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
|
||||
; RUN: | FileCheck -check-prefix=RV32IFD %s
|
||||
|
||||
define double @select_fcmp_false(double %a, double %b) nounwind {
|
||||
; RV32IFD-LABEL: select_fcmp_false:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: mv a0, a2
|
||||
; RV32IFD-NEXT: mv a1, a3
|
||||
; RV32IFD-NEXT: ret
|
||||
%1 = fcmp false double %a, %b
|
||||
%2 = select i1 %1, double %a, double %b
|
||||
ret double %2
|
||||
}
|
||||
|
||||
define double @select_fcmp_oeq(double %a, double %b) nounwind {
|
||||
; RV32IFD-LABEL: select_fcmp_oeq:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: sw a2, 8(sp)
|
||||
; RV32IFD-NEXT: sw a3, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a1, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft1, 8(sp)
|
||||
; RV32IFD-NEXT: feq.d a0, ft1, ft0
|
||||
; RV32IFD-NEXT: bnez a0, .LBB1_2
|
||||
; RV32IFD-NEXT: # %bb.1:
|
||||
; RV32IFD-NEXT: fmv.d ft1, ft0
|
||||
; RV32IFD-NEXT: .LBB1_2:
|
||||
; RV32IFD-NEXT: fsd ft1, 8(sp)
|
||||
; RV32IFD-NEXT: lw a0, 8(sp)
|
||||
; RV32IFD-NEXT: lw a1, 12(sp)
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
%1 = fcmp oeq double %a, %b
|
||||
%2 = select i1 %1, double %a, double %b
|
||||
ret double %2
|
||||
}
|
||||
|
||||
define double @select_fcmp_ogt(double %a, double %b) nounwind {
|
||||
; RV32IFD-LABEL: select_fcmp_ogt:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: sw a0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a1, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a2, 8(sp)
|
||||
; RV32IFD-NEXT: sw a3, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft1, 8(sp)
|
||||
; RV32IFD-NEXT: flt.d a0, ft1, ft0
|
||||
; RV32IFD-NEXT: bnez a0, .LBB2_2
|
||||
; RV32IFD-NEXT: # %bb.1:
|
||||
; RV32IFD-NEXT: fmv.d ft0, ft1
|
||||
; RV32IFD-NEXT: .LBB2_2:
|
||||
; RV32IFD-NEXT: fsd ft0, 8(sp)
|
||||
; RV32IFD-NEXT: lw a0, 8(sp)
|
||||
; RV32IFD-NEXT: lw a1, 12(sp)
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
%1 = fcmp ogt double %a, %b
|
||||
%2 = select i1 %1, double %a, double %b
|
||||
ret double %2
|
||||
}
|
||||
|
||||
define double @select_fcmp_oge(double %a, double %b) nounwind {
|
||||
; RV32IFD-LABEL: select_fcmp_oge:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: sw a0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a1, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a2, 8(sp)
|
||||
; RV32IFD-NEXT: sw a3, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft1, 8(sp)
|
||||
; RV32IFD-NEXT: fle.d a0, ft1, ft0
|
||||
; RV32IFD-NEXT: bnez a0, .LBB3_2
|
||||
; RV32IFD-NEXT: # %bb.1:
|
||||
; RV32IFD-NEXT: fmv.d ft0, ft1
|
||||
; RV32IFD-NEXT: .LBB3_2:
|
||||
; RV32IFD-NEXT: fsd ft0, 8(sp)
|
||||
; RV32IFD-NEXT: lw a0, 8(sp)
|
||||
; RV32IFD-NEXT: lw a1, 12(sp)
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
%1 = fcmp oge double %a, %b
|
||||
%2 = select i1 %1, double %a, double %b
|
||||
ret double %2
|
||||
}
|
||||
|
||||
define double @select_fcmp_olt(double %a, double %b) nounwind {
|
||||
; RV32IFD-LABEL: select_fcmp_olt:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: sw a2, 8(sp)
|
||||
; RV32IFD-NEXT: sw a3, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a1, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft1, 8(sp)
|
||||
; RV32IFD-NEXT: flt.d a0, ft1, ft0
|
||||
; RV32IFD-NEXT: bnez a0, .LBB4_2
|
||||
; RV32IFD-NEXT: # %bb.1:
|
||||
; RV32IFD-NEXT: fmv.d ft1, ft0
|
||||
; RV32IFD-NEXT: .LBB4_2:
|
||||
; RV32IFD-NEXT: fsd ft1, 8(sp)
|
||||
; RV32IFD-NEXT: lw a0, 8(sp)
|
||||
; RV32IFD-NEXT: lw a1, 12(sp)
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
%1 = fcmp olt double %a, %b
|
||||
%2 = select i1 %1, double %a, double %b
|
||||
ret double %2
|
||||
}
|
||||
|
||||
define double @select_fcmp_ole(double %a, double %b) nounwind {
|
||||
; RV32IFD-LABEL: select_fcmp_ole:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: sw a2, 8(sp)
|
||||
; RV32IFD-NEXT: sw a3, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a1, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft1, 8(sp)
|
||||
; RV32IFD-NEXT: fle.d a0, ft1, ft0
|
||||
; RV32IFD-NEXT: bnez a0, .LBB5_2
|
||||
; RV32IFD-NEXT: # %bb.1:
|
||||
; RV32IFD-NEXT: fmv.d ft1, ft0
|
||||
; RV32IFD-NEXT: .LBB5_2:
|
||||
; RV32IFD-NEXT: fsd ft1, 8(sp)
|
||||
; RV32IFD-NEXT: lw a0, 8(sp)
|
||||
; RV32IFD-NEXT: lw a1, 12(sp)
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
%1 = fcmp ole double %a, %b
|
||||
%2 = select i1 %1, double %a, double %b
|
||||
ret double %2
|
||||
}
|
||||
|
||||
define double @select_fcmp_one(double %a, double %b) nounwind {
|
||||
; TODO: feq.s+sltiu+bne sequence could be optimised
|
||||
; RV32IFD-LABEL: select_fcmp_one:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: sw a0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a1, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a2, 8(sp)
|
||||
; RV32IFD-NEXT: sw a3, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft1, 8(sp)
|
||||
; RV32IFD-NEXT: feq.d a0, ft1, ft1
|
||||
; RV32IFD-NEXT: feq.d a1, ft0, ft0
|
||||
; RV32IFD-NEXT: and a0, a1, a0
|
||||
; RV32IFD-NEXT: feq.d a1, ft0, ft1
|
||||
; RV32IFD-NEXT: not a1, a1
|
||||
; RV32IFD-NEXT: seqz a0, a0
|
||||
; RV32IFD-NEXT: xori a0, a0, 1
|
||||
; RV32IFD-NEXT: and a0, a1, a0
|
||||
; RV32IFD-NEXT: bnez a0, .LBB6_2
|
||||
; RV32IFD-NEXT: # %bb.1:
|
||||
; RV32IFD-NEXT: fmv.d ft0, ft1
|
||||
; RV32IFD-NEXT: .LBB6_2:
|
||||
; RV32IFD-NEXT: fsd ft0, 8(sp)
|
||||
; RV32IFD-NEXT: lw a0, 8(sp)
|
||||
; RV32IFD-NEXT: lw a1, 12(sp)
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
%1 = fcmp one double %a, %b
|
||||
%2 = select i1 %1, double %a, double %b
|
||||
ret double %2
|
||||
}
|
||||
|
||||
define double @select_fcmp_ord(double %a, double %b) nounwind {
|
||||
; RV32IFD-LABEL: select_fcmp_ord:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: sw a0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a1, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a2, 8(sp)
|
||||
; RV32IFD-NEXT: sw a3, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft1, 8(sp)
|
||||
; RV32IFD-NEXT: feq.d a0, ft1, ft1
|
||||
; RV32IFD-NEXT: feq.d a1, ft0, ft0
|
||||
; RV32IFD-NEXT: and a0, a1, a0
|
||||
; RV32IFD-NEXT: seqz a0, a0
|
||||
; RV32IFD-NEXT: xori a0, a0, 1
|
||||
; RV32IFD-NEXT: bnez a0, .LBB7_2
|
||||
; RV32IFD-NEXT: # %bb.1:
|
||||
; RV32IFD-NEXT: fmv.d ft0, ft1
|
||||
; RV32IFD-NEXT: .LBB7_2:
|
||||
; RV32IFD-NEXT: fsd ft0, 8(sp)
|
||||
; RV32IFD-NEXT: lw a0, 8(sp)
|
||||
; RV32IFD-NEXT: lw a1, 12(sp)
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
%1 = fcmp ord double %a, %b
|
||||
%2 = select i1 %1, double %a, double %b
|
||||
ret double %2
|
||||
}
|
||||
|
||||
define double @select_fcmp_ueq(double %a, double %b) nounwind {
|
||||
; RV32IFD-LABEL: select_fcmp_ueq:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: sw a0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a1, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a2, 8(sp)
|
||||
; RV32IFD-NEXT: sw a3, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft1, 8(sp)
|
||||
; RV32IFD-NEXT: feq.d a0, ft1, ft1
|
||||
; RV32IFD-NEXT: feq.d a1, ft0, ft0
|
||||
; RV32IFD-NEXT: and a0, a1, a0
|
||||
; RV32IFD-NEXT: seqz a0, a0
|
||||
; RV32IFD-NEXT: feq.d a1, ft0, ft1
|
||||
; RV32IFD-NEXT: or a0, a1, a0
|
||||
; RV32IFD-NEXT: bnez a0, .LBB8_2
|
||||
; RV32IFD-NEXT: # %bb.1:
|
||||
; RV32IFD-NEXT: fmv.d ft0, ft1
|
||||
; RV32IFD-NEXT: .LBB8_2:
|
||||
; RV32IFD-NEXT: fsd ft0, 8(sp)
|
||||
; RV32IFD-NEXT: lw a0, 8(sp)
|
||||
; RV32IFD-NEXT: lw a1, 12(sp)
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
%1 = fcmp ueq double %a, %b
|
||||
%2 = select i1 %1, double %a, double %b
|
||||
ret double %2
|
||||
}
|
||||
|
||||
define double @select_fcmp_ugt(double %a, double %b) nounwind {
|
||||
; RV32IFD-LABEL: select_fcmp_ugt:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: sw a2, 8(sp)
|
||||
; RV32IFD-NEXT: sw a3, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a1, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft1, 8(sp)
|
||||
; RV32IFD-NEXT: fle.d a0, ft1, ft0
|
||||
; RV32IFD-NEXT: xori a0, a0, 1
|
||||
; RV32IFD-NEXT: bnez a0, .LBB9_2
|
||||
; RV32IFD-NEXT: # %bb.1:
|
||||
; RV32IFD-NEXT: fmv.d ft1, ft0
|
||||
; RV32IFD-NEXT: .LBB9_2:
|
||||
; RV32IFD-NEXT: fsd ft1, 8(sp)
|
||||
; RV32IFD-NEXT: lw a0, 8(sp)
|
||||
; RV32IFD-NEXT: lw a1, 12(sp)
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
%1 = fcmp ugt double %a, %b
|
||||
%2 = select i1 %1, double %a, double %b
|
||||
ret double %2
|
||||
}
|
||||
|
||||
define double @select_fcmp_uge(double %a, double %b) nounwind {
|
||||
; RV32IFD-LABEL: select_fcmp_uge:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: sw a2, 8(sp)
|
||||
; RV32IFD-NEXT: sw a3, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a1, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft1, 8(sp)
|
||||
; RV32IFD-NEXT: flt.d a0, ft1, ft0
|
||||
; RV32IFD-NEXT: xori a0, a0, 1
|
||||
; RV32IFD-NEXT: bnez a0, .LBB10_2
|
||||
; RV32IFD-NEXT: # %bb.1:
|
||||
; RV32IFD-NEXT: fmv.d ft1, ft0
|
||||
; RV32IFD-NEXT: .LBB10_2:
|
||||
; RV32IFD-NEXT: fsd ft1, 8(sp)
|
||||
; RV32IFD-NEXT: lw a0, 8(sp)
|
||||
; RV32IFD-NEXT: lw a1, 12(sp)
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
%1 = fcmp uge double %a, %b
|
||||
%2 = select i1 %1, double %a, double %b
|
||||
ret double %2
|
||||
}
|
||||
|
||||
define double @select_fcmp_ult(double %a, double %b) nounwind {
|
||||
; RV32IFD-LABEL: select_fcmp_ult:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: sw a0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a1, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a2, 8(sp)
|
||||
; RV32IFD-NEXT: sw a3, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft1, 8(sp)
|
||||
; RV32IFD-NEXT: fle.d a0, ft1, ft0
|
||||
; RV32IFD-NEXT: xori a0, a0, 1
|
||||
; RV32IFD-NEXT: bnez a0, .LBB11_2
|
||||
; RV32IFD-NEXT: # %bb.1:
|
||||
; RV32IFD-NEXT: fmv.d ft0, ft1
|
||||
; RV32IFD-NEXT: .LBB11_2:
|
||||
; RV32IFD-NEXT: fsd ft0, 8(sp)
|
||||
; RV32IFD-NEXT: lw a0, 8(sp)
|
||||
; RV32IFD-NEXT: lw a1, 12(sp)
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
%1 = fcmp ult double %a, %b
|
||||
%2 = select i1 %1, double %a, double %b
|
||||
ret double %2
|
||||
}
|
||||
|
||||
define double @select_fcmp_ule(double %a, double %b) nounwind {
|
||||
; RV32IFD-LABEL: select_fcmp_ule:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: sw a0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a1, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a2, 8(sp)
|
||||
; RV32IFD-NEXT: sw a3, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft1, 8(sp)
|
||||
; RV32IFD-NEXT: flt.d a0, ft1, ft0
|
||||
; RV32IFD-NEXT: xori a0, a0, 1
|
||||
; RV32IFD-NEXT: bnez a0, .LBB12_2
|
||||
; RV32IFD-NEXT: # %bb.1:
|
||||
; RV32IFD-NEXT: fmv.d ft0, ft1
|
||||
; RV32IFD-NEXT: .LBB12_2:
|
||||
; RV32IFD-NEXT: fsd ft0, 8(sp)
|
||||
; RV32IFD-NEXT: lw a0, 8(sp)
|
||||
; RV32IFD-NEXT: lw a1, 12(sp)
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
%1 = fcmp ule double %a, %b
|
||||
%2 = select i1 %1, double %a, double %b
|
||||
ret double %2
|
||||
}
|
||||
|
||||
define double @select_fcmp_une(double %a, double %b) nounwind {
|
||||
; RV32IFD-LABEL: select_fcmp_une:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: sw a2, 8(sp)
|
||||
; RV32IFD-NEXT: sw a3, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a1, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft1, 8(sp)
|
||||
; RV32IFD-NEXT: feq.d a0, ft1, ft0
|
||||
; RV32IFD-NEXT: xori a0, a0, 1
|
||||
; RV32IFD-NEXT: bnez a0, .LBB13_2
|
||||
; RV32IFD-NEXT: # %bb.1:
|
||||
; RV32IFD-NEXT: fmv.d ft1, ft0
|
||||
; RV32IFD-NEXT: .LBB13_2:
|
||||
; RV32IFD-NEXT: fsd ft1, 8(sp)
|
||||
; RV32IFD-NEXT: lw a0, 8(sp)
|
||||
; RV32IFD-NEXT: lw a1, 12(sp)
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
%1 = fcmp une double %a, %b
|
||||
%2 = select i1 %1, double %a, double %b
|
||||
ret double %2
|
||||
}
|
||||
|
||||
define double @select_fcmp_uno(double %a, double %b) nounwind {
|
||||
; TODO: sltiu+bne could be optimized
|
||||
; RV32IFD-LABEL: select_fcmp_uno:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: sw a0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a1, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a2, 8(sp)
|
||||
; RV32IFD-NEXT: sw a3, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft1, 8(sp)
|
||||
; RV32IFD-NEXT: feq.d a0, ft1, ft1
|
||||
; RV32IFD-NEXT: feq.d a1, ft0, ft0
|
||||
; RV32IFD-NEXT: and a0, a1, a0
|
||||
; RV32IFD-NEXT: seqz a0, a0
|
||||
; RV32IFD-NEXT: bnez a0, .LBB14_2
|
||||
; RV32IFD-NEXT: # %bb.1:
|
||||
; RV32IFD-NEXT: fmv.d ft0, ft1
|
||||
; RV32IFD-NEXT: .LBB14_2:
|
||||
; RV32IFD-NEXT: fsd ft0, 8(sp)
|
||||
; RV32IFD-NEXT: lw a0, 8(sp)
|
||||
; RV32IFD-NEXT: lw a1, 12(sp)
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
%1 = fcmp uno double %a, %b
|
||||
%2 = select i1 %1, double %a, double %b
|
||||
ret double %2
|
||||
}
|
||||
|
||||
define double @select_fcmp_true(double %a, double %b) nounwind {
|
||||
; RV32IFD-LABEL: select_fcmp_true:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: ret
|
||||
%1 = fcmp true double %a, %b
|
||||
%2 = select i1 %1, double %a, double %b
|
||||
ret double %2
|
||||
}
|
||||
|
||||
; Ensure that ISel succeeds for a select+fcmp that has an i32 result type.
|
||||
define i32 @i32_select_fcmp_oeq(double %a, double %b, i32 %c, i32 %d) nounwind {
|
||||
; RV32IFD-LABEL: i32_select_fcmp_oeq:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: sw a2, 8(sp)
|
||||
; RV32IFD-NEXT: sw a3, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a0, 8(sp)
|
||||
; RV32IFD-NEXT: sw a1, 12(sp)
|
||||
; RV32IFD-NEXT: fld ft1, 8(sp)
|
||||
; RV32IFD-NEXT: feq.d a0, ft1, ft0
|
||||
; RV32IFD-NEXT: bnez a0, .LBB16_2
|
||||
; RV32IFD-NEXT: # %bb.1:
|
||||
; RV32IFD-NEXT: mv a4, a5
|
||||
; RV32IFD-NEXT: .LBB16_2:
|
||||
; RV32IFD-NEXT: mv a0, a4
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
%1 = fcmp oeq double %a, %b
|
||||
%2 = select i1 %1, i32 %c, i32 %d
|
||||
ret i32 %2
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user