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Tidy some more comments and whitespace.
llvm-svn: 99081
This commit is contained in:
Bob Wilson
parent
7dacf6bb70
commit
e70bdcb2a7
@ -384,64 +384,61 @@ def VLD4q32odd_UPD : VLD4DWB<0b0001, 0b1000, "32">;
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// VLD2LN : Vector Load (single 2-element structure to one lane)
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class VLD2LN<bits<4> op11_8, string Dt>
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: NLdSt<1,0b10,op11_8,{?,?,?,?}, (outs DPR:$dst1, DPR:$dst2),
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(ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
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IIC_VLD2, "vld2", Dt, "\\{$dst1[$lane], $dst2[$lane]\\}, $addr",
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"$src1 = $dst1, $src2 = $dst2", []>;
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: NLdSt<1, 0b10, op11_8, {?,?,?,?}, (outs DPR:$dst1, DPR:$dst2),
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(ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
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IIC_VLD2, "vld2", Dt, "\\{$dst1[$lane], $dst2[$lane]\\}, $addr",
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"$src1 = $dst1, $src2 = $dst2", []>;
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// vld2 to single-spaced registers.
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def VLD2LNd8 : VLD2LN<0b0001, "8">;
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def VLD2LNd16 : VLD2LN<0b0101, "16"> { let Inst{5} = 0; }
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def VLD2LNd32 : VLD2LN<0b1001, "32"> { let Inst{6} = 0; }
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// vld2 to double-spaced even registers.
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// ...with double-spaced registers:
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def VLD2LNq16 : VLD2LN<0b0101, "16"> { let Inst{5} = 1; }
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def VLD2LNq32 : VLD2LN<0b1001, "32"> { let Inst{6} = 1; }
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// vld2 to double-spaced odd registers.
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// ...alternate versions to be allocated odd register numbers:
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def VLD2LNq16odd : VLD2LN<0b0101, "16"> { let Inst{5} = 1; }
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def VLD2LNq32odd : VLD2LN<0b1001, "32"> { let Inst{6} = 1; }
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// VLD3LN : Vector Load (single 3-element structure to one lane)
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class VLD3LN<bits<4> op11_8, string Dt>
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: NLdSt<1,0b10,op11_8,{?,?,?,?}, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
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(ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
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nohash_imm:$lane), IIC_VLD3, "vld3", Dt,
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"\\{$dst1[$lane], $dst2[$lane], $dst3[$lane]\\}, $addr",
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"$src1 = $dst1, $src2 = $dst2, $src3 = $dst3", []>;
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: NLdSt<1, 0b10, op11_8, {?,?,?,?}, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
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(ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
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nohash_imm:$lane), IIC_VLD3, "vld3", Dt,
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"\\{$dst1[$lane], $dst2[$lane], $dst3[$lane]\\}, $addr",
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"$src1 = $dst1, $src2 = $dst2, $src3 = $dst3", []>;
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// vld3 to single-spaced registers.
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def VLD3LNd8 : VLD3LN<0b0010, "8"> { let Inst{4} = 0; }
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def VLD3LNd16 : VLD3LN<0b0110, "16"> { let Inst{5-4} = 0b00; }
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def VLD3LNd32 : VLD3LN<0b1010, "32"> { let Inst{6-4} = 0b000; }
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// vld3 to double-spaced even registers.
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// ...with double-spaced registers:
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def VLD3LNq16 : VLD3LN<0b0110, "16"> { let Inst{5-4} = 0b10; }
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def VLD3LNq32 : VLD3LN<0b1010, "32"> { let Inst{6-4} = 0b100; }
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// vld3 to double-spaced odd registers.
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// ...alternate versions to be allocated odd register numbers:
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def VLD3LNq16odd : VLD3LN<0b0110, "16"> { let Inst{5-4} = 0b10; }
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def VLD3LNq32odd : VLD3LN<0b1010, "32"> { let Inst{6-4} = 0b100; }
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// VLD4LN : Vector Load (single 4-element structure to one lane)
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class VLD4LN<bits<4> op11_8, string Dt>
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: NLdSt<1,0b10,op11_8,{?,?,?,?},
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(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
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(ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
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nohash_imm:$lane), IIC_VLD4, "vld4", Dt,
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: NLdSt<1, 0b10, op11_8, {?,?,?,?},
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(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
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(ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
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nohash_imm:$lane), IIC_VLD4, "vld4", Dt,
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"\\{$dst1[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $addr",
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"$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>;
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"$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>;
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// vld4 to single-spaced registers.
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def VLD4LNd8 : VLD4LN<0b0011, "8">;
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def VLD4LNd16 : VLD4LN<0b0111, "16"> { let Inst{5} = 0; }
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def VLD4LNd32 : VLD4LN<0b1011, "32"> { let Inst{6} = 0; }
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// vld4 to double-spaced even registers.
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// ...with double-spaced registers:
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def VLD4LNq16 : VLD4LN<0b0111, "16"> { let Inst{5} = 1; }
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def VLD4LNq32 : VLD4LN<0b1011, "32"> { let Inst{6} = 1; }
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// vld4 to double-spaced odd registers.
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// ...alternate versions to be allocated odd register numbers:
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def VLD4LNq16odd : VLD4LN<0b0111, "16"> { let Inst{5} = 1; }
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def VLD4LNq32odd : VLD4LN<0b1011, "32"> { let Inst{6} = 1; }
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@ -597,62 +594,59 @@ def VST4q32odd_UPD : VST4WB<0b1000, "32">;
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// VST2LN : Vector Store (single 2-element structure from one lane)
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class VST2LN<bits<4> op11_8, string Dt>
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: NLdSt<1,0b00,op11_8,{?,?,?,?}, (outs),
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: NLdSt<1, 0b00, op11_8, {?,?,?,?}, (outs),
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(ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
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IIC_VST, "vst2", Dt, "\\{$src1[$lane], $src2[$lane]\\}, $addr",
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"", []>;
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// vst2 to single-spaced registers.
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def VST2LNd8 : VST2LN<0b0001, "8">;
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def VST2LNd16 : VST2LN<0b0101, "16"> { let Inst{5} = 0; }
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def VST2LNd32 : VST2LN<0b1001, "32"> { let Inst{6} = 0; }
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// vst2 to double-spaced even registers.
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// ...with double-spaced registers:
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def VST2LNq16 : VST2LN<0b0101, "16"> { let Inst{5} = 1; }
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def VST2LNq32 : VST2LN<0b1001, "32"> { let Inst{6} = 1; }
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// vst2 to double-spaced odd registers.
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// ...alternate versions to be allocated odd register numbers:
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def VST2LNq16odd : VST2LN<0b0101, "16"> { let Inst{5} = 1; }
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def VST2LNq32odd : VST2LN<0b1001, "32"> { let Inst{6} = 1; }
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// VST3LN : Vector Store (single 3-element structure from one lane)
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class VST3LN<bits<4> op11_8, string Dt>
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: NLdSt<1,0b00,op11_8,{?,?,?,?}, (outs),
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: NLdSt<1, 0b00, op11_8, {?,?,?,?}, (outs),
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(ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
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nohash_imm:$lane), IIC_VST, "vst3", Dt,
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"\\{$src1[$lane], $src2[$lane], $src3[$lane]\\}, $addr", "", []>;
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// vst3 to single-spaced registers.
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def VST3LNd8 : VST3LN<0b0010, "8"> { let Inst{4} = 0; }
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def VST3LNd16 : VST3LN<0b0110, "16"> { let Inst{5-4} = 0b00; }
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def VST3LNd32 : VST3LN<0b1010, "32"> { let Inst{6-4} = 0b000; }
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// vst3 to double-spaced even registers.
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// ...with double-spaced registers:
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def VST3LNq16 : VST3LN<0b0110, "16"> { let Inst{5-4} = 0b10; }
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def VST3LNq32 : VST3LN<0b1010, "32"> { let Inst{6-4} = 0b100; }
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// vst3 to double-spaced odd registers.
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// ...alternate versions to be allocated odd register numbers:
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def VST3LNq16odd : VST3LN<0b0110, "16"> { let Inst{5-4} = 0b10; }
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def VST3LNq32odd : VST3LN<0b1010, "32"> { let Inst{6-4} = 0b100; }
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// VST4LN : Vector Store (single 4-element structure from one lane)
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class VST4LN<bits<4> op11_8, string Dt>
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: NLdSt<1,0b00,op11_8,{?,?,?,?}, (outs),
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: NLdSt<1, 0b00, op11_8, {?,?,?,?}, (outs),
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(ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
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nohash_imm:$lane), IIC_VST, "vst4", Dt,
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"\\{$src1[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $addr",
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"", []>;
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// vst4 to single-spaced registers.
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def VST4LNd8 : VST4LN<0b0011, "8">;
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def VST4LNd16 : VST4LN<0b0111, "16"> { let Inst{5} = 0; }
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def VST4LNd32 : VST4LN<0b1011, "32"> { let Inst{6} = 0; }
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// vst4 to double-spaced even registers.
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// ...with double-spaced registers:
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def VST4LNq16 : VST4LN<0b0111, "16"> { let Inst{5} = 1; }
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def VST4LNq32 : VST4LN<0b1011, "32"> { let Inst{6} = 1; }
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// vst4 to double-spaced odd registers.
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// ...alternate versions to be allocated odd register numbers:
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def VST4LNq16odd : VST4LN<0b0111, "16"> { let Inst{5} = 1; }
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def VST4LNq32odd : VST4LN<0b1011, "32"> { let Inst{6} = 1; }
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