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[Hexagon] Add support to handle bit-reverse load intrinsics
Patch by Sumanth Gundapaneni. llvm-svn: 328774
This commit is contained in:
Krzysztof Parzyszek
parent
13e9d4c9ef
commit
e739d778c4
@ -643,41 +643,6 @@ class Hexagon_df_dfdfdfqi_Intrinsic<string GCCIntSuffix>
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// This one below will not be auto-generated,
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// so make sure, you don't overwrite this one.
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//
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// BUILTIN_INFO(SI_to_SXTHI_asrh,SI_ftype_SI,1)
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//
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def int_hexagon_SI_to_SXTHI_asrh :
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Hexagon_si_si_Intrinsic<"SI_to_SXTHI_asrh">;
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//
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// BUILTIN_INFO_NONCONST(brev_ldd,PTR_ftype_PTRPTRSI,3)
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//
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def int_hexagon_brev_ldd :
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Hexagon_mem_memmemsi_Intrinsic<"brev_ldd">;
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//
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// BUILTIN_INFO_NONCONST(brev_ldw,PTR_ftype_PTRPTRSI,3)
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//
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def int_hexagon_brev_ldw :
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Hexagon_mem_memmemsi_Intrinsic<"brev_ldw">;
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//
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// BUILTIN_INFO_NONCONST(brev_ldh,PTR_ftype_PTRPTRSI,3)
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//
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def int_hexagon_brev_ldh :
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Hexagon_mem_memmemsi_Intrinsic<"brev_ldh">;
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//
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// BUILTIN_INFO_NONCONST(brev_lduh,PTR_ftype_PTRPTRSI,3)
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//
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def int_hexagon_brev_lduh :
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Hexagon_mem_memmemsi_Intrinsic<"brev_lduh">;
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//
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// BUILTIN_INFO_NONCONST(brev_ldb,PTR_ftype_PTRPTRSI,3)
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//
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def int_hexagon_brev_ldb :
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Hexagon_mem_memmemsi_Intrinsic<"brev_ldb">;
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//
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// BUILTIN_INFO_NONCONST(brev_ldub,PTR_ftype_PTRPTRSI,3)
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//
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def int_hexagon_brev_ldub :
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Hexagon_mem_memmemsi_Intrinsic<"brev_ldub">;
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//
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// BUILTIN_INFO_NONCONST(circ_ldd,PTR_ftype_PTRPTRSISI,4)
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//
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def int_hexagon_circ_ldd :
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@ -708,31 +673,6 @@ Hexagon_mem_memmemsisi_Intrinsic<"circ_ldb">;
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def int_hexagon_circ_ldub :
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Hexagon_mem_memmemsisi_Intrinsic<"circ_ldub">;
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//
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// BUILTIN_INFO_NONCONST(brev_stb,PTR_ftype_PTRSISI,3)
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//
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def int_hexagon_brev_stb :
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Hexagon_mem_memsisi_Intrinsic<"brev_stb">;
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//
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// BUILTIN_INFO_NONCONST(brev_sthhi,PTR_ftype_PTRSISI,3)
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//
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def int_hexagon_brev_sthhi :
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Hexagon_mem_memsisi_Intrinsic<"brev_sthhi">;
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//
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// BUILTIN_INFO_NONCONST(brev_sth,PTR_ftype_PTRSISI,3)
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//
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def int_hexagon_brev_sth :
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Hexagon_mem_memsisi_Intrinsic<"brev_sth">;
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//
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// BUILTIN_INFO_NONCONST(brev_stw,PTR_ftype_PTRSISI,3)
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//
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def int_hexagon_brev_stw :
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Hexagon_mem_memsisi_Intrinsic<"brev_stw">;
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//
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// BUILTIN_INFO_NONCONST(brev_std,PTR_ftype_PTRSISI,3)
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//
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def int_hexagon_brev_std :
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Hexagon_mem_memdisi_Intrinsic<"brev_std">;
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//
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// BUILTIN_INFO_NONCONST(circ_std,PTR_ftype_PTRDISISI,4)
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//
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@ -9340,6 +9280,27 @@ defm int_hexagon_S2_storerf : Hexagon_custom_circ_st_Intrinsic<llvm_i32_ty>;
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defm int_hexagon_S2_storeri : Hexagon_custom_circ_st_Intrinsic<llvm_i32_ty>;
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defm int_hexagon_S2_storerd : Hexagon_custom_circ_st_Intrinsic<llvm_i64_ty>;
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// The front-end emits the intrinsic call with only two arguments. The third
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// argument from the builtin is already used by front-end to write to memory
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// by generating a store.
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class Hexagon_custom_brev_ld_Intrinsic<LLVMType ElTy>
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: Hexagon_NonGCC_Intrinsic<
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[ElTy, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty],
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[IntrReadMem]>;
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def int_hexagon_L2_loadrub_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>;
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def int_hexagon_L2_loadrb_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>;
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def int_hexagon_L2_loadruh_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>;
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def int_hexagon_L2_loadrh_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>;
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def int_hexagon_L2_loadri_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>;
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def int_hexagon_L2_loadrd_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i64_ty>;
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def int_hexagon_S2_storerb_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_stb">;
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def int_hexagon_S2_storerh_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_sth">;
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def int_hexagon_S2_storerf_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_sthhi">;
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def int_hexagon_S2_storeri_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_stw">;
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def int_hexagon_S2_storerd_pbr : Hexagon_mem_memdisi_Intrinsic<"brev_std">;
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///
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/// HexagonV62 intrinsics
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@ -210,26 +210,6 @@ MachineSDNode *HexagonDAGToDAGISel::LoadInstrForLoadIntrinsic(SDNode *IntN) {
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return Res;
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}
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static std::map<unsigned,unsigned> LoadPbrMap = {
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{ Intrinsic::hexagon_brev_ldb, Hexagon::L2_loadrb_pbr },
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{ Intrinsic::hexagon_brev_ldub, Hexagon::L2_loadrub_pbr },
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{ Intrinsic::hexagon_brev_ldh, Hexagon::L2_loadrh_pbr },
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{ Intrinsic::hexagon_brev_lduh, Hexagon::L2_loadruh_pbr },
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{ Intrinsic::hexagon_brev_ldw, Hexagon::L2_loadri_pbr },
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{ Intrinsic::hexagon_brev_ldd, Hexagon::L2_loadrd_pbr },
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};
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auto FLB = LoadPbrMap.find(IntNo);
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if (FLB != LoadPbrMap.end()) {
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SDNode *Mod = CurDAG->getMachineNode(Hexagon::A2_tfrrcr, dl, MVT::i32,
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IntN->getOperand(4));
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EVT ValTy = (IntNo == Intrinsic::hexagon_brev_ldd) ? MVT::i64 : MVT::i32;
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EVT RTys[] = { ValTy, MVT::i32, MVT::Other };
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// Operands: { Base, Modifier, Chain }
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MachineSDNode *Res = CurDAG->getMachineNode(FLB->second, dl, RTys,
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{ IntN->getOperand(2), SDValue(Mod,0), IntN->getOperand(0) });
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return Res;
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}
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return nullptr;
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}
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@ -300,14 +280,10 @@ bool HexagonDAGToDAGISel::tryLoadOfLoadIntrinsic(LoadSDNode *N) {
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// a sign-extending intrinsic into (or the other way around).
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ISD::LoadExtType IntExt;
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switch (cast<ConstantSDNode>(C->getOperand(1))->getZExtValue()) {
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case Intrinsic::hexagon_brev_ldub:
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case Intrinsic::hexagon_brev_lduh:
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case Intrinsic::hexagon_circ_ldub:
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case Intrinsic::hexagon_circ_lduh:
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IntExt = ISD::ZEXTLOAD;
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break;
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case Intrinsic::hexagon_brev_ldw:
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case Intrinsic::hexagon_brev_ldd:
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case Intrinsic::hexagon_circ_ldw:
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case Intrinsic::hexagon_circ_ldd:
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IntExt = ISD::NON_EXTLOAD;
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@ -338,6 +314,47 @@ bool HexagonDAGToDAGISel::tryLoadOfLoadIntrinsic(LoadSDNode *N) {
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return false;
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}
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// Convert the bit-reverse load intrinsic to appropriate target instruction.
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bool HexagonDAGToDAGISel::SelectBrevLdIntrinsic(SDNode *IntN) {
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if (IntN->getOpcode() != ISD::INTRINSIC_W_CHAIN)
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return false;
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const SDLoc &dl(IntN);
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unsigned IntNo = cast<ConstantSDNode>(IntN->getOperand(1))->getZExtValue();
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static const std::map<unsigned, unsigned> LoadBrevMap = {
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{ Intrinsic::hexagon_L2_loadrb_pbr, Hexagon::L2_loadrb_pbr },
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{ Intrinsic::hexagon_L2_loadrub_pbr, Hexagon::L2_loadrub_pbr },
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{ Intrinsic::hexagon_L2_loadrh_pbr, Hexagon::L2_loadrh_pbr },
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{ Intrinsic::hexagon_L2_loadruh_pbr, Hexagon::L2_loadruh_pbr },
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{ Intrinsic::hexagon_L2_loadri_pbr, Hexagon::L2_loadri_pbr },
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{ Intrinsic::hexagon_L2_loadrd_pbr, Hexagon::L2_loadrd_pbr }
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};
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auto FLI = LoadBrevMap.find(IntNo);
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if (FLI != LoadBrevMap.end()) {
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EVT ValTy =
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(IntNo == Intrinsic::hexagon_L2_loadrd_pbr) ? MVT::i64 : MVT::i32;
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EVT RTys[] = { ValTy, MVT::i32, MVT::Other };
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// Operands of Intrinsic: {chain, enum ID of intrinsic, baseptr,
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// modifier}.
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// Operands of target instruction: { Base, Modifier, Chain }.
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MachineSDNode *Res = CurDAG->getMachineNode(
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FLI->second, dl, RTys,
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{IntN->getOperand(2), IntN->getOperand(3), IntN->getOperand(0)});
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MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
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MemOp[0] = cast<MemIntrinsicSDNode>(IntN)->getMemOperand();
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Res->setMemRefs(MemOp, MemOp + 1);
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ReplaceUses(SDValue(IntN, 0), SDValue(Res, 0));
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ReplaceUses(SDValue(IntN, 1), SDValue(Res, 1));
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ReplaceUses(SDValue(IntN, 2), SDValue(Res, 2));
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CurDAG->RemoveDeadNode(IntN);
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return true;
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}
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return false;
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}
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/// Generate a machine instruction node for the new circlar buffer intrinsics.
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/// The new versions use a CSx register instead of the K field.
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bool HexagonDAGToDAGISel::SelectNewCircIntrinsic(SDNode *IntN) {
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@ -612,6 +629,10 @@ void HexagonDAGToDAGISel::SelectIntrinsicWChain(SDNode *N) {
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return;
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}
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// Handle bit-reverse load intrinsics.
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if (SelectBrevLdIntrinsic(N))
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return;
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if (SelectNewCircIntrinsic(N))
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return;
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@ -90,6 +90,7 @@ public:
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unsigned ConstraintID,
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std::vector<SDValue> &OutOps) override;
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bool tryLoadOfLoadIntrinsic(LoadSDNode *N);
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bool SelectBrevLdIntrinsic(SDNode *IntN);
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bool SelectNewCircIntrinsic(SDNode *IntN);
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void SelectLoad(SDNode *N);
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void SelectIndexedLoad(LoadSDNode *LD, const SDLoc &dl);
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@ -39,6 +39,7 @@
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#include "llvm/IR/InlineAsm.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/IR/Intrinsics.h"
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#include "llvm/IR/IntrinsicInst.h"
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#include "llvm/IR/Module.h"
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#include "llvm/IR/Type.h"
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#include "llvm/IR/Value.h"
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@ -1744,6 +1745,81 @@ const char* HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const {
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return nullptr;
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}
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// Bit-reverse Load Intrinsic: Check if the instruction is a bit reverse load
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// intrinsic.
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static bool isBrevLdIntrinsic(const Value *Inst) {
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unsigned ID = cast<IntrinsicInst>(Inst)->getIntrinsicID();
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return (ID == Intrinsic::hexagon_L2_loadrd_pbr ||
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ID == Intrinsic::hexagon_L2_loadri_pbr ||
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ID == Intrinsic::hexagon_L2_loadrh_pbr ||
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ID == Intrinsic::hexagon_L2_loadruh_pbr ||
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ID == Intrinsic::hexagon_L2_loadrb_pbr ||
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ID == Intrinsic::hexagon_L2_loadrub_pbr);
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}
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// Bit-reverse Load Intrinsic :Crawl up and figure out the object from previous
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// instruction. So far we only handle bitcast, extract value and bit reverse
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// load intrinsic instructions. Should we handle CGEP ?
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static Value *getBrevLdObject(Value *V) {
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if (Operator::getOpcode(V) == Instruction::ExtractValue ||
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Operator::getOpcode(V) == Instruction::BitCast)
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V = cast<Operator>(V)->getOperand(0);
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else if (isa<IntrinsicInst>(V) && isBrevLdIntrinsic(V))
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V = cast<Instruction>(V)->getOperand(0);
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return V;
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}
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// Bit-reverse Load Intrinsic: For a PHI Node return either an incoming edge or
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// a back edge. If the back edge comes from the intrinsic itself, the incoming
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// edge is returned.
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static Value *returnEdge(const PHINode *PN, Value *IntrBaseVal) {
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const BasicBlock *Parent = PN->getParent();
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int Idx = -1;
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for (unsigned i = 0, e = PN->getNumIncomingValues(); i < e; ++i) {
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BasicBlock *Blk = PN->getIncomingBlock(i);
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// Determine if the back edge is originated from intrinsic.
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if (Blk == Parent) {
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Value *BackEdgeVal = PN->getIncomingValue(i);
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Value *BaseVal;
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// Loop over till we return the same Value or we hit the IntrBaseVal.
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do {
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BaseVal = BackEdgeVal;
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BackEdgeVal = getBrevLdObject(BackEdgeVal);
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} while ((BaseVal != BackEdgeVal) && (IntrBaseVal != BackEdgeVal));
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// If the getBrevLdObject returns IntrBaseVal, we should return the
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// incoming edge.
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if (IntrBaseVal == BackEdgeVal)
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continue;
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Idx = i;
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break;
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} else // Set the node to incoming edge.
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Idx = i;
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}
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assert(Idx >= 0 && "Unexpected index to incoming argument in PHI");
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return PN->getIncomingValue(Idx);
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}
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// Bit-reverse Load Intrinsic: Figure out the underlying object the base
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// pointer points to, for the bit-reverse load intrinsic. Setting this to
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// memoperand might help alias analysis to figure out the dependencies.
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static Value *getUnderLyingObjectForBrevLdIntr(Value *V) {
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Value *IntrBaseVal = V;
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Value *BaseVal;
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// Loop over till we return the same Value, implies we either figure out
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// the object or we hit a PHI
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do {
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BaseVal = V;
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V = getBrevLdObject(V);
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} while (BaseVal != V);
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// Identify the object from PHINode.
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if (const PHINode *PN = dyn_cast<PHINode>(V))
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return returnEdge(PN, IntrBaseVal);
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// For non PHI nodes, the object is the last value returned by getBrevLdObject
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else
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return V;
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}
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/// Given an intrinsic, checks if on the target the intrinsic will need to map
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/// to a MemIntrinsicNode (touches memory). If this is the case, it returns
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/// true and store the intrinsic information into the IntrinsicInfo that was
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@ -1753,6 +1829,32 @@ bool HexagonTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
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MachineFunction &MF,
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unsigned Intrinsic) const {
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switch (Intrinsic) {
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case Intrinsic::hexagon_L2_loadrd_pbr:
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case Intrinsic::hexagon_L2_loadri_pbr:
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case Intrinsic::hexagon_L2_loadrh_pbr:
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case Intrinsic::hexagon_L2_loadruh_pbr:
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case Intrinsic::hexagon_L2_loadrb_pbr:
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case Intrinsic::hexagon_L2_loadrub_pbr: {
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Info.opc = ISD::INTRINSIC_W_CHAIN;
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auto &DL = I.getCalledFunction()->getParent()->getDataLayout();
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auto &Cont = I.getCalledFunction()->getParent()->getContext();
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// The intrinsic function call is of the form { ElTy, i8* }
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// @llvm.hexagon.L2.loadXX.pbr(i8*, i32). The pointer and memory access type
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// should be derived from ElTy.
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PointerType *PtrTy = I.getCalledFunction()
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->getReturnType()
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->getContainedType(0)
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->getPointerTo();
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Info.memVT = MVT::getVT(PtrTy->getElementType());
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llvm::Value *BasePtrVal = I.getOperand(0);
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Info.ptrVal = getUnderLyingObjectForBrevLdIntr(BasePtrVal);
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// The offset value comes through Modifier register. For now, assume the
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// offset is 0.
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Info.offset = 0;
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Info.align = DL.getABITypeAlignment(Info.memVT.getTypeForEVT(Cont));
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Info.flags = MachineMemOperand::MOLoad;
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return true;
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}
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case Intrinsic::hexagon_V6_vgathermw:
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case Intrinsic::hexagon_V6_vgathermw_128B:
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case Intrinsic::hexagon_V6_vgathermh:
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@ -807,7 +807,6 @@ def : T_QII_pat<C2_muxii, int_hexagon_C2_muxii, s32_0ImmPred, s8_0ImmPred>;
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// Shift halfword
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def : T_R_pat<A2_aslh, int_hexagon_A2_aslh>;
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def : T_R_pat<A2_asrh, int_hexagon_A2_asrh>;
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def : T_R_pat<A2_asrh, int_hexagon_SI_to_SXTHI_asrh>;
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// Sign/zero extend
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def : T_R_pat<A2_sxth, int_hexagon_A2_sxth>;
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@ -1353,11 +1352,11 @@ class T_stb_pat <InstHexagon MI, Intrinsic IntID, PatLeaf Val>
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: Pat<(IntID I32:$Rs, Val:$Rt, I32:$Ru),
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(MI I32:$Rs, I32:$Ru, Val:$Rt)>;
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def : T_stb_pat <S2_storerh_pbr, int_hexagon_brev_sth, I32>;
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def : T_stb_pat <S2_storerb_pbr, int_hexagon_brev_stb, I32>;
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def : T_stb_pat <S2_storeri_pbr, int_hexagon_brev_stw, I32>;
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def : T_stb_pat <S2_storerf_pbr, int_hexagon_brev_sthhi, I32>;
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def : T_stb_pat <S2_storerd_pbr, int_hexagon_brev_std, I64>;
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def : T_stb_pat <S2_storerh_pbr, int_hexagon_S2_storerh_pbr, I32>;
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def : T_stb_pat <S2_storerb_pbr, int_hexagon_S2_storerb_pbr, I32>;
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def : T_stb_pat <S2_storeri_pbr, int_hexagon_S2_storeri_pbr, I32>;
|
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def : T_stb_pat <S2_storerf_pbr, int_hexagon_S2_storerf_pbr, I32>;
|
||||
def : T_stb_pat <S2_storerd_pbr, int_hexagon_S2_storerd_pbr, I64>;
|
||||
|
||||
class T_stc_pat <InstHexagon MI, Intrinsic IntID, PatLeaf Imm, PatLeaf Val>
|
||||
: Pat<(IntID I32:$Rs, Val:$Rt, I32:$Ru, Imm:$s),
|
||||
|
||||
@ -15,126 +15,78 @@
|
||||
; r1 = memub(r0++m0:brev)
|
||||
; r1 = memb(r0++m0:brev)
|
||||
|
||||
target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
|
||||
target triple = "hexagon"
|
||||
target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
|
||||
target triple = "hexagon-unknown--elf"
|
||||
|
||||
define i64 @foo(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind {
|
||||
; CHECK: @call_brev_ldd
|
||||
define i64* @call_brev_ldd(i64* %ptr, i64 %dst, i32 %mod) local_unnamed_addr #0 {
|
||||
entry:
|
||||
%inputLR = alloca i64, align 8
|
||||
%conv = zext i16 %filtMemLen to i32
|
||||
%shr1 = lshr i32 %conv, 1
|
||||
%idxprom = sext i16 %filtMemIndex to i32
|
||||
%arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
|
||||
%0 = bitcast i16* %arrayidx to i8*
|
||||
%1 = bitcast i64* %inputLR to i8*
|
||||
%sub = sub i32 13, %shr1
|
||||
%shl = shl i32 1, %sub
|
||||
%0 = bitcast i64* %ptr to i8*
|
||||
; CHECK: = memd(r{{[0-9]*}}++m{{[0-1]}}:brev)
|
||||
%2 = call i8* @llvm.hexagon.brev.ldd(i8* %0, i8* %1, i32 %shl)
|
||||
%3 = bitcast i8* %1 to i64*
|
||||
%4 = load i64, i64* %3, align 8, !tbaa !0
|
||||
ret i64 %4
|
||||
%1 = tail call { i64, i8* } @llvm.hexagon.L2.loadrd.pbr(i8* %0, i32 %mod)
|
||||
%2 = extractvalue { i64, i8* } %1, 1
|
||||
%3 = bitcast i8* %2 to i64*
|
||||
ret i64* %3
|
||||
}
|
||||
|
||||
declare i8* @llvm.hexagon.brev.ldd(i8*, i8*, i32) nounwind
|
||||
|
||||
define i32 @foo1(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind {
|
||||
; CHECK: @call_brev_ldw
|
||||
define i32* @call_brev_ldw(i32* %ptr, i32 %dst, i32 %mod) local_unnamed_addr #0 {
|
||||
entry:
|
||||
%inputLR = alloca i32, align 4
|
||||
%conv = zext i16 %filtMemLen to i32
|
||||
%shr1 = lshr i32 %conv, 1
|
||||
%idxprom = sext i16 %filtMemIndex to i32
|
||||
%arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
|
||||
%0 = bitcast i16* %arrayidx to i8*
|
||||
%1 = bitcast i32* %inputLR to i8*
|
||||
%sub = sub i32 14, %shr1
|
||||
%shl = shl i32 1, %sub
|
||||
%0 = bitcast i32* %ptr to i8*
|
||||
; CHECK: = memw(r{{[0-9]*}}++m{{[0-1]}}:brev)
|
||||
%2 = call i8* @llvm.hexagon.brev.ldw(i8* %0, i8* %1, i32 %shl)
|
||||
%3 = bitcast i8* %1 to i32*
|
||||
%4 = load i32, i32* %3, align 4, !tbaa !2
|
||||
ret i32 %4
|
||||
%1 = tail call { i32, i8* } @llvm.hexagon.L2.loadri.pbr(i8* %0, i32 %mod)
|
||||
%2 = extractvalue { i32, i8* } %1, 1
|
||||
%3 = bitcast i8* %2 to i32*
|
||||
ret i32* %3
|
||||
}
|
||||
|
||||
declare i8* @llvm.hexagon.brev.ldw(i8*, i8*, i32) nounwind
|
||||
|
||||
define signext i16 @foo2(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind {
|
||||
; CHECK: @call_brev_ldh
|
||||
define i16* @call_brev_ldh(i16* %ptr, i16 signext %dst, i32 %mod) local_unnamed_addr #0 {
|
||||
entry:
|
||||
%inputLR = alloca i16, align 2
|
||||
%conv = zext i16 %filtMemLen to i32
|
||||
%shr1 = lshr i32 %conv, 1
|
||||
%idxprom = sext i16 %filtMemIndex to i32
|
||||
%arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
|
||||
%0 = bitcast i16* %arrayidx to i8*
|
||||
%1 = bitcast i16* %inputLR to i8*
|
||||
%sub = sub i32 15, %shr1
|
||||
%shl = shl i32 1, %sub
|
||||
; CHECK: = memh(r{{[0-9]*}}++m0:brev)
|
||||
%2 = call i8* @llvm.hexagon.brev.ldh(i8* %0, i8* %1, i32 %shl)
|
||||
%3 = bitcast i8* %1 to i16*
|
||||
%4 = load i16, i16* %3, align 2, !tbaa !3
|
||||
ret i16 %4
|
||||
%0 = bitcast i16* %ptr to i8*
|
||||
; CHECK: = memh(r{{[0-9]*}}++m{{[0-1]}}:brev)
|
||||
%1 = tail call { i32, i8* } @llvm.hexagon.L2.loadrh.pbr(i8* %0, i32 %mod)
|
||||
%2 = extractvalue { i32, i8* } %1, 1
|
||||
%3 = bitcast i8* %2 to i16*
|
||||
ret i16* %3
|
||||
}
|
||||
|
||||
declare i8* @llvm.hexagon.brev.ldh(i8*, i8*, i32) nounwind
|
||||
|
||||
define zeroext i16 @foo3(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind {
|
||||
; CHECK: @call_brev_lduh
|
||||
define i16* @call_brev_lduh(i16* %ptr, i16 zeroext %dst, i32 %mod) local_unnamed_addr #0 {
|
||||
entry:
|
||||
%inputLR = alloca i16, align 2
|
||||
%conv = zext i16 %filtMemLen to i32
|
||||
%shr1 = lshr i32 %conv, 1
|
||||
%idxprom = sext i16 %filtMemIndex to i32
|
||||
%arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
|
||||
%0 = bitcast i16* %arrayidx to i8*
|
||||
%1 = bitcast i16* %inputLR to i8*
|
||||
%sub = sub i32 15, %shr1
|
||||
%shl = shl i32 1, %sub
|
||||
; CHECK: = memuh(r{{[0-9]*}}++m0:brev)
|
||||
%2 = call i8* @llvm.hexagon.brev.lduh(i8* %0, i8* %1, i32 %shl)
|
||||
%3 = bitcast i8* %1 to i16*
|
||||
%4 = load i16, i16* %3, align 2, !tbaa !3
|
||||
ret i16 %4
|
||||
%0 = bitcast i16* %ptr to i8*
|
||||
; CHECK: = memuh(r{{[0-9]*}}++m{{[0-1]}}:brev)
|
||||
%1 = tail call { i32, i8* } @llvm.hexagon.L2.loadruh.pbr(i8* %0, i32 %mod)
|
||||
%2 = extractvalue { i32, i8* } %1, 1
|
||||
%3 = bitcast i8* %2 to i16*
|
||||
ret i16* %3
|
||||
}
|
||||
|
||||
declare i8* @llvm.hexagon.brev.lduh(i8*, i8*, i32) nounwind
|
||||
|
||||
define zeroext i8 @foo4(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind {
|
||||
; CHECK: @call_brev_ldb
|
||||
define i8* @call_brev_ldb(i8* %ptr, i8 signext %dst, i32 %mod) local_unnamed_addr #0 {
|
||||
entry:
|
||||
%inputLR = alloca i8, align 1
|
||||
%conv = zext i16 %filtMemLen to i32
|
||||
%shr1 = lshr i32 %conv, 1
|
||||
%idxprom = sext i16 %filtMemIndex to i32
|
||||
%arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
|
||||
%0 = bitcast i16* %arrayidx to i8*
|
||||
%sub = sub nsw i32 16, %shr1
|
||||
%shl = shl i32 1, %sub
|
||||
; CHECK: = memub(r{{[0-9]*}}++m{{[0-1]}}:brev)
|
||||
%1 = call i8* @llvm.hexagon.brev.ldub(i8* %0, i8* %inputLR, i32 %shl)
|
||||
%2 = load i8, i8* %inputLR, align 1, !tbaa !0
|
||||
ret i8 %2
|
||||
}
|
||||
|
||||
declare i8* @llvm.hexagon.brev.ldub(i8*, i8*, i32) nounwind
|
||||
|
||||
define signext i8 @foo5(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind {
|
||||
entry:
|
||||
%inputLR = alloca i8, align 1
|
||||
%conv = zext i16 %filtMemLen to i32
|
||||
%shr1 = lshr i32 %conv, 1
|
||||
%idxprom = sext i16 %filtMemIndex to i32
|
||||
%arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
|
||||
%0 = bitcast i16* %arrayidx to i8*
|
||||
%sub = sub nsw i32 16, %shr1
|
||||
%shl = shl i32 1, %sub
|
||||
; CHECK: = memb(r{{[0-9]*}}++m{{[0-1]}}:brev)
|
||||
%1 = call i8* @llvm.hexagon.brev.ldb(i8* %0, i8* %inputLR, i32 %shl)
|
||||
%2 = load i8, i8* %inputLR, align 1, !tbaa !0
|
||||
ret i8 %2
|
||||
%0 = tail call { i32, i8* } @llvm.hexagon.L2.loadrb.pbr(i8* %ptr, i32 %mod)
|
||||
%1 = extractvalue { i32, i8* } %0, 1
|
||||
ret i8* %1
|
||||
}
|
||||
|
||||
declare i8* @llvm.hexagon.brev.ldb(i8*, i8*, i32) nounwind
|
||||
; Function Attrs: nounwind readonly
|
||||
; CHECK: @call_brev_ldub
|
||||
define i8* @call_brev_ldub(i8* %ptr, i8 zeroext %dst, i32 %mod) local_unnamed_addr #0 {
|
||||
entry:
|
||||
; CHECK: = memub(r{{[0-9]*}}++m{{[0-1]}}:brev)
|
||||
%0 = tail call { i32, i8* } @llvm.hexagon.L2.loadrub.pbr(i8* %ptr, i32 %mod)
|
||||
%1 = extractvalue { i32, i8* } %0, 1
|
||||
ret i8* %1
|
||||
}
|
||||
|
||||
!0 = !{!"omnipotent char", !1}
|
||||
!1 = !{!"Simple C/C++ TBAA"}
|
||||
!2 = !{!"int", !0}
|
||||
!3 = !{!"short", !0}
|
||||
declare { i64, i8* } @llvm.hexagon.L2.loadrd.pbr(i8*, i32) #1
|
||||
declare { i32, i8* } @llvm.hexagon.L2.loadri.pbr(i8*, i32) #1
|
||||
declare { i32, i8* } @llvm.hexagon.L2.loadrh.pbr(i8*, i32) #1
|
||||
declare { i32, i8* } @llvm.hexagon.L2.loadruh.pbr(i8*, i32) #1
|
||||
declare { i32, i8* } @llvm.hexagon.L2.loadrb.pbr(i8*, i32) #1
|
||||
declare { i32, i8* } @llvm.hexagon.L2.loadrub.pbr(i8*, i32) #1
|
||||
|
||||
attributes #0 = { nounwind readonly "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx-double,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" }
|
||||
attributes #1 = { nounwind readonly }
|
||||
|
||||
@ -27,11 +27,11 @@ entry:
|
||||
%sub = sub i32 13, %shr2
|
||||
%shl = shl i32 1, %sub
|
||||
; CHECK: memd(r{{[0-9]*}}++m{{[0-1]}}:brev)
|
||||
%1 = tail call i8* @llvm.hexagon.brev.std(i8* %0, i64 undef, i32 %shl)
|
||||
%1 = tail call i8* @llvm.hexagon.S2.storerd.pbr(i8* %0, i64 undef, i32 %shl)
|
||||
ret i64 0
|
||||
}
|
||||
|
||||
declare i8* @llvm.hexagon.brev.std(i8*, i64, i32) nounwind
|
||||
declare i8* @llvm.hexagon.S2.storerd.pbr(i8*, i64, i32) nounwind
|
||||
|
||||
define i32 @foo1(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind {
|
||||
entry:
|
||||
@ -43,11 +43,11 @@ entry:
|
||||
%sub = sub i32 14, %shr1
|
||||
%shl = shl i32 1, %sub
|
||||
; CHECK: memw(r{{[0-9]*}}++m{{[0-1]}}:brev)
|
||||
%1 = tail call i8* @llvm.hexagon.brev.stw(i8* %0, i32 undef, i32 %shl)
|
||||
%1 = tail call i8* @llvm.hexagon.S2.storeri.pbr(i8* %0, i32 undef, i32 %shl)
|
||||
ret i32 0
|
||||
}
|
||||
|
||||
declare i8* @llvm.hexagon.brev.stw(i8*, i32, i32) nounwind
|
||||
declare i8* @llvm.hexagon.S2.storeri.pbr(i8*, i32, i32) nounwind
|
||||
|
||||
define signext i16 @foo2(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind {
|
||||
entry:
|
||||
@ -59,11 +59,11 @@ entry:
|
||||
%sub = sub i32 15, %shr2
|
||||
%shl = shl i32 1, %sub
|
||||
; CHECK: memh(r{{[0-9]*}}++m{{[0-1]}}:brev)
|
||||
%1 = tail call i8* @llvm.hexagon.brev.sth(i8* %0, i32 0, i32 %shl)
|
||||
%1 = tail call i8* @llvm.hexagon.S2.storerh.pbr(i8* %0, i32 0, i32 %shl)
|
||||
ret i16 0
|
||||
}
|
||||
|
||||
declare i8* @llvm.hexagon.brev.sth(i8*, i32, i32) nounwind
|
||||
declare i8* @llvm.hexagon.S2.storerh.pbr(i8*, i32, i32) nounwind
|
||||
|
||||
define signext i16 @foo3(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind {
|
||||
entry:
|
||||
@ -75,11 +75,11 @@ entry:
|
||||
%sub = sub i32 15, %shr2
|
||||
%shl = shl i32 1, %sub
|
||||
; CHECK: memh(r{{[0-9]*}}++m{{[0-1]}}:brev) = r{{[0-9]*}}.h
|
||||
%1 = tail call i8* @llvm.hexagon.brev.sthhi(i8* %0, i32 0, i32 %shl)
|
||||
%1 = tail call i8* @llvm.hexagon.S2.storerf.pbr(i8* %0, i32 0, i32 %shl)
|
||||
ret i16 0
|
||||
}
|
||||
|
||||
declare i8* @llvm.hexagon.brev.sthhi(i8*, i32, i32) nounwind
|
||||
declare i8* @llvm.hexagon.S2.storerf.pbr(i8*, i32, i32) nounwind
|
||||
|
||||
define zeroext i8 @foo5(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind {
|
||||
entry:
|
||||
@ -91,11 +91,11 @@ entry:
|
||||
%sub = sub nsw i32 16, %shr2
|
||||
; CHECK: memb(r{{[0-9]*}}++m{{[0-1]}}:brev)
|
||||
%shl = shl i32 1, %sub
|
||||
%1 = tail call i8* @llvm.hexagon.brev.stb(i8* %0, i32 0, i32 %shl)
|
||||
%1 = tail call i8* @llvm.hexagon.S2.storerb.pbr(i8* %0, i32 0, i32 %shl)
|
||||
ret i8 0
|
||||
}
|
||||
|
||||
declare i8* @llvm.hexagon.brev.stb(i8*, i32, i32) nounwind
|
||||
declare i8* @llvm.hexagon.S2.storerb.pbr(i8*, i32, i32) nounwind
|
||||
|
||||
!0 = !{!"omnipotent char", !1}
|
||||
!1 = !{!"Simple C/C++ TBAA"}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user