From e747b10bc3aa5122a7dfbe1255dfab42c52d83c8 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Sat, 10 Oct 2009 21:40:13 +0000 Subject: [PATCH] more updates llvm-svn: 83735 --- docs/ReleaseNotes-2.6.html | 107 ++++++++++++++++++++++--------------- 1 file changed, 64 insertions(+), 43 deletions(-) diff --git a/docs/ReleaseNotes-2.6.html b/docs/ReleaseNotes-2.6.html index 9b00ab51183..2a86a9c5067 100644 --- a/docs/ReleaseNotes-2.6.html +++ b/docs/ReleaseNotes-2.6.html @@ -553,6 +553,30 @@ release includes a few major enhancements and additions to the optimizers:

+ + +
+Interpreter and JIT Improvements +
+ +
+ + + +
+
Target Independent Code Generator Improvements @@ -579,7 +603,7 @@ it run faster:

  • The Machine Sinking pass is now enabled by default. This pass moves side-effect free operations down the CFG so that they are executed on fewer paths through a function.
    • -
  • The code generator now performs "Stack slot coloring" of register spills, +
  • The code generator now performs "stack slot coloring" of register spills, which allows spill slots to be reused. This leads to smaller stack frames in cases where there are lots of register spills.
  • The register allocator has many improvements to take better advantage of @@ -594,7 +618,10 @@ it run faster:

  • The instruction selector is better at propagating information about values (such as whether they are sign/zero extended etc) across basic block boundaries.
    • -
  • SelectionDAGS: New BuildVectorSDNode (r65296), and ISD::VECTOR_SHUFFLE (r69952 / PR2957)
    • +
  • The SelectionDAG datastructure has new nodes for representing buildvector + and vector shuffle operations. This + makes operations and pattern matching more efficient and easier to get + right.
  • The Prolog/Epilog Insertion Pass now has experimental support for performing the "shrink wrapping" optimization, which moves spills and reloads around in the CFG to avoid doing saves on paths that don't need them.
    • @@ -622,15 +649,28 @@ it run faster:

    @@ -675,16 +715,19 @@ it run faster:

  • Preliminary support for processors, such as the Cortex-A8 and Cortex-A9, that implement version v7-A of the ARM architecture. The ARM backend now -supports both the Thumb2 and Advanced SIMD (Neon) instruction sets. The -AAPCS-VFP "hard float" calling conventions are also supported with the --float-abi=hard flag. These features are still somewhat experimental -and subject to change. The Neon intrinsics, in particular, may change in future -releases of LLVM. +supports both the Thumb2 and Advanced SIMD (Neon) instruction sets.
    • + +
  • The AAPCS-VFP "hard float" calling conventions are also supported with the +-float-abi=hard flag.
    • + +
  • The ARM calling convention code is now tblgen generated instead of C++ + code.
    • - ARM AAPCS-VFP hard float ABI is supported. - ARM calling convention code is now tblgen generated instead of manual. - ARM: NEON support. neonfp for doing single precision fp with neon instead of VFP. + +

    These features are still somewhat experimental +and subject to change. The Neon intrinsics, in particular, may change in future +releases of LLVM.

    @@ -709,28 +752,6 @@ releases of LLVM.
    - -
    -Interpreter and JIT Improvements -
    - -
    - - - -
    - -
    New Useful APIs @@ -739,7 +760,7 @@ releases of LLVM.
      -
    • New EngineBuilder class for creating JITs: r76276
      • +
    • New PrettyStackTrace, crashes of llvm tools should give some indication of what the compiler was doing at the time of the crash (e.g. running a pass), and print out command line arguments. StringRef class, Twine class. New WeakVH and AssertingVH and CallbackVH classes. @@ -748,7 +769,7 @@ releases of LLVM. New llvm/System/Atomic.h, llvm/System/RWMutex.h for portable atomic ops, rw locks. New SourceMgr, SMLoc classes for simple parsers with caret diagnostics and #include support, (used by tablegen, llvm-mc, the .ll parser, FileCheck, etc) - +