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Also combine zext/sext into selects for ARM.
This turns common i1 patterns into predicated instructions:
(add (zext cc), x) -> (select cc (add x, 1), x)
(add (sext cc), x) -> (select cc (add x, -1), x)
For a function like:
unsigned f(unsigned s, int x) {
return s + (x>0);
}
We now produce:
cmp r1, #0
it gt
addgt.w r0, r0, #1
Instead of:
movs r2, #0
cmp r1, #0
it gt
movgt r2, #1
add r0, r2
llvm-svn: 162177
This commit is contained in:
Jakob Stoklund Olesen
parent
ece4a53017
commit
e78d4a5b08
@ -6981,6 +6981,65 @@ static inline bool isZeroOrAllOnes(SDValue N, bool AllOnes) {
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return AllOnes ? C->isAllOnesValue() : C->isNullValue();
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}
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// Return true if N is conditionally 0 or all ones.
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// Detects these expressions where cc is an i1 value:
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//
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// (select cc 0, y) [AllOnes=0]
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// (select cc y, 0) [AllOnes=0]
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// (zext cc) [AllOnes=0]
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// (sext cc) [AllOnes=0/1]
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// (select cc -1, y) [AllOnes=1]
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// (select cc y, -1) [AllOnes=1]
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//
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// Invert is set when N is the null/all ones constant when CC is false.
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// OtherOp is set to the alternative value of N.
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static bool isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes,
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SDValue &CC, bool &Invert,
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SDValue &OtherOp,
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SelectionDAG &DAG) {
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switch (N->getOpcode()) {
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default: return false;
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case ISD::SELECT: {
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CC = N->getOperand(0);
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SDValue N1 = N->getOperand(1);
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SDValue N2 = N->getOperand(2);
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if (isZeroOrAllOnes(N1, AllOnes)) {
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Invert = false;
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OtherOp = N2;
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return true;
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}
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if (isZeroOrAllOnes(N2, AllOnes)) {
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Invert = true;
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OtherOp = N1;
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return true;
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}
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return false;
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}
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case ISD::ZERO_EXTEND:
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// (zext cc) can never be the all ones value.
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if (AllOnes)
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return false;
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// Fall through.
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case ISD::SIGN_EXTEND: {
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EVT VT = N->getValueType(0);
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CC = N->getOperand(0);
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if (CC.getValueType() != MVT::i1)
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return false;
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Invert = !AllOnes;
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if (AllOnes)
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// When looking for an AllOnes constant, N is an sext, and the 'other'
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// value is 0.
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OtherOp = DAG.getConstant(0, VT);
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else if (N->getOpcode() == ISD::ZERO_EXTEND)
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// When looking for a 0 constant, N can be zext or sext.
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OtherOp = DAG.getConstant(1, VT);
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else
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OtherOp = DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT);
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return true;
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}
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}
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}
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// Combine a constant select operand into its use:
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//
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// (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
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@ -6992,6 +7051,13 @@ static inline bool isZeroOrAllOnes(SDValue N, bool AllOnes) {
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// The transform is rejected if the select doesn't have a constant operand that
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// is null, or all ones when AllOnes is set.
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//
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// Also recognize sext/zext from i1:
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//
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// (add (zext cc), x) -> (select cc (add x, 1), x)
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// (add (sext cc), x) -> (select cc (add x, -1), x)
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//
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// These transformations eventually create predicated instructions.
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//
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// @param N The node to transform.
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// @param Slct The N operand that is a select.
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// @param OtherOp The other N operand (x above).
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@ -7003,53 +7069,24 @@ SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
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TargetLowering::DAGCombinerInfo &DCI,
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bool AllOnes = false) {
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SelectionDAG &DAG = DCI.DAG;
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const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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EVT VT = N->getValueType(0);
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unsigned Opc = N->getOpcode();
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bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
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SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
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SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
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ISD::CondCode CC = ISD::SETCC_INVALID;
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if (isSlctCC) {
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CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
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} else {
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SDValue CCOp = Slct.getOperand(0);
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if (CCOp.getOpcode() == ISD::SETCC)
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CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
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}
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bool DoXform = false;
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bool InvCC = false;
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if (isZeroOrAllOnes(LHS, AllOnes)) {
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DoXform = true;
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} else if (CC != ISD::SETCC_INVALID && isZeroOrAllOnes(RHS, AllOnes)) {
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std::swap(LHS, RHS);
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SDValue Op0 = Slct.getOperand(0);
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EVT OpVT = isSlctCC ? Op0.getValueType() : Op0.getOperand(0).getValueType();
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bool isInt = OpVT.isInteger();
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CC = ISD::getSetCCInverse(CC, isInt);
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if (!TLI.isCondCodeLegal(CC, OpVT))
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return SDValue(); // Inverse operator isn't legal.
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DoXform = true;
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InvCC = true;
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}
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if (!DoXform)
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SDValue NonConstantVal;
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SDValue CCOp;
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bool SwapSelectOps;
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if (!isConditionalZeroOrAllOnes(Slct.getNode(), AllOnes, CCOp, SwapSelectOps,
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NonConstantVal, DAG))
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return SDValue();
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SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
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if (isSlctCC)
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return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
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Slct.getOperand(0), Slct.getOperand(1), CC);
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SDValue CCOp = Slct.getOperand(0);
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if (InvCC)
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CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
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CCOp.getOperand(0), CCOp.getOperand(1), CC);
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// Slct is now know to be the desired identity constant when CC is true.
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SDValue TrueVal = OtherOp;
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SDValue FalseVal = DAG.getNode(N->getOpcode(), N->getDebugLoc(), VT,
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OtherOp, NonConstantVal);
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// Unless SwapSelectOps says CC should be false.
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if (SwapSelectOps)
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std::swap(TrueVal, FalseVal);
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return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
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CCOp, OtherOp, Result);
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CCOp, TrueVal, FalseVal);
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}
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// Attempt combineSelectAndUse on each operand of a commutative operator N.
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@ -7058,12 +7095,12 @@ SDValue combineSelectAndUseCommutative(SDNode *N, bool AllOnes,
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TargetLowering::DAGCombinerInfo &DCI) {
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SDValue N0 = N->getOperand(0);
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SDValue N1 = N->getOperand(1);
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if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
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if (N0.getNode()->hasOneUse()) {
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SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes);
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if (Result.getNode())
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return Result;
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}
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if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
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if (N1.getNode()->hasOneUse()) {
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SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes);
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if (Result.getNode())
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return Result;
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@ -7174,7 +7211,7 @@ static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
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return Result;
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// fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
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if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
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if (N0.getNode()->hasOneUse()) {
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SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
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if (Result.getNode()) return Result;
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}
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@ -7206,7 +7243,7 @@ static SDValue PerformSUBCombine(SDNode *N,
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SDValue N1 = N->getOperand(1);
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// fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
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if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
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if (N1.getNode()->hasOneUse()) {
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SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
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if (Result.getNode()) return Result;
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}
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@ -190,3 +190,35 @@ define void @pr13628() nounwind uwtable align 2 {
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ret void
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}
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declare void @bar(i8*)
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; Fold zext i1 into predicated add
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define i32 @t13(i32 %c, i32 %a) nounwind readnone ssp {
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entry:
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; ARM: t13
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; ARM: cmp r1, #10
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; ARM: addgt r0, r0, #1
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; T2: t13
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; T2: cmp r1, #10
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; T2: addgt.w r0, r0, #1
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%cmp = icmp sgt i32 %a, 10
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%conv = zext i1 %cmp to i32
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%add = add i32 %conv, %c
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ret i32 %add
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}
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; Fold sext i1 into predicated sub
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define i32 @t14(i32 %c, i32 %a) nounwind readnone ssp {
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entry:
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; ARM: t14
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; ARM: cmp r1, #10
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; ARM: subgt r0, r0, #1
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; T2: t14
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; T2: cmp r1, #10
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; T2: subgt.w r0, r0, #1
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%cmp = icmp sgt i32 %a, 10
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%conv = sext i1 %cmp to i32
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%add = add i32 %conv, %c
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ret i32 %add
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}
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