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[X86][SSE] Add support for combining target shuffles to PSLLDQ/PSRLDQ byte shifts
llvm-svn: 278502
This commit is contained in:
Simon Pilgrim
parent
f06744fc0b
commit
e7b88298e9
@ -4257,6 +4257,16 @@ static bool isSequentialOrUndefOrZeroInRange(ArrayRef<int> Mask, unsigned Pos,
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return true;
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}
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/// Return true if every element in Mask, beginning
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/// from position Pos and ending in Pos+Size is undef or is zero.
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static bool isUndefOrZeroInRange(ArrayRef<int> Mask, unsigned Pos,
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unsigned Size) {
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for (unsigned i = Pos, e = Pos + Size; i != e; ++i)
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if (!isUndefOrZero(Mask[i]))
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return false;
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return true;
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}
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/// Return true if the specified EXTRACT_SUBVECTOR operand specifies a vector
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/// extract that is suitable for instruction that extract 128 or 256 bit vectors
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static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
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@ -24849,6 +24859,57 @@ static bool matchUnaryPermuteVectorShuffle(MVT MaskVT, ArrayRef<int> Mask,
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const X86Subtarget &Subtarget,
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unsigned &Shuffle, MVT &ShuffleVT,
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unsigned &PermuteImm) {
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unsigned NumMaskElts = Mask.size();
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unsigned NumLanes = MaskVT.getSizeInBits() / 128;
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unsigned NumEltsPerLane = NumMaskElts / NumLanes;
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bool FloatDomain = MaskVT.isFloatingPoint();
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// Attempt to match against PSLLDQ/PSRLDQ byte shifts.
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// TODO: Share common code with lowerVectorShuffleAsShift?
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//
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// PSLLDQ : (little-endian) left byte shift
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// [ zz, 0, 1, 2, 3, 4, 5, 6]
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// [ zz, zz, -1, -1, 2, 3, 4, -1]
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// [ zz, zz, zz, zz, zz, zz, -1, 1]
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// PSRLDQ : (little-endian) right byte shift
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// [ 5, 6, 7, zz, zz, zz, zz, zz]
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// [ -1, 5, 6, 7, zz, zz, zz, zz]
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// [ 1, 2, -1, -1, -1, -1, zz, zz]
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if (!FloatDomain && ((MaskVT.is128BitVector() && Subtarget.hasSSE2()) ||
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(MaskVT.is256BitVector() && Subtarget.hasAVX2()))) {
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for (unsigned Shift = 1; Shift != NumEltsPerLane; ++Shift) {
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bool IsVSHLDQ = true;
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bool IsVSRLDQ = true;
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for (unsigned Lane = 0; Lane != NumLanes; ++Lane) {
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unsigned Base = Lane * NumEltsPerLane;
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unsigned Ofs = NumEltsPerLane - Shift;
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IsVSHLDQ &= isUndefOrZeroInRange(Mask, Base, Shift);
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IsVSHLDQ &= isSequentialOrUndefInRange(Mask, Base + Shift, Ofs, Base);
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IsVSRLDQ &= isUndefOrZeroInRange(Mask, Base + Ofs, Shift);
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IsVSRLDQ &= isSequentialOrUndefInRange(Mask, Base, Ofs, Base + Shift);
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if (!IsVSHLDQ && !IsVSRLDQ)
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break;
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}
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if (IsVSHLDQ) {
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Shuffle = X86ISD::VSHLDQ;
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ShuffleVT = MVT::getVectorVT(MVT::i8, NumLanes * 16);
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PermuteImm = Shift * (MaskVT.getScalarSizeInBits() / 8);
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return true;
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}
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if (IsVSRLDQ) {
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Shuffle = X86ISD::VSRLDQ;
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ShuffleVT = MVT::getVectorVT(MVT::i8, NumLanes * 16);
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PermuteImm = Shift * (MaskVT.getScalarSizeInBits() / 8);
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return true;
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}
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}
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}
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// Ensure we don't contain any zero elements.
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for (int M : Mask) {
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if (M == SM_SentinelZero)
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@ -24902,7 +24963,6 @@ static bool matchUnaryPermuteVectorShuffle(MVT MaskVT, ArrayRef<int> Mask,
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// AVX introduced the VPERMILPD/VPERMILPS float permutes, before then we
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// had to use 2-input SHUFPD/SHUFPS shuffles (not handled here).
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bool FloatDomain = MaskVT.isFloatingPoint();
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if (FloatDomain && !Subtarget.hasAVX())
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return false;
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@ -480,7 +480,7 @@ define <16 x i8> @insert_v16i8_z123456789ABZDEz(<16 x i8> %a) {
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; SSSE3-NEXT: pshufb {{.*#+}} xmm2 = xmm2[0],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
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; SSSE3-NEXT: por %xmm2, %xmm0
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; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14],zero
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; SSSE3-NEXT: pshufb {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0]
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; SSSE3-NEXT: pslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0]
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; SSSE3-NEXT: por %xmm1, %xmm0
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; SSSE3-NEXT: retq
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;
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@ -560,7 +560,7 @@ define <32 x i8> @insert_v32i8_z123456789ABCDEzGHIJKLMNOPQRSTzz(<32 x i8> %a) {
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; SSSE3-NEXT: movdqa {{.*#+}} xmm3 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,128]
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; SSSE3-NEXT: pshufb %xmm3, %xmm0
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; SSSE3-NEXT: movdqa %xmm2, %xmm4
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; SSSE3-NEXT: pshufb {{.*#+}} xmm4 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm4[0]
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; SSSE3-NEXT: pslldq {{.*#+}} xmm4 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm4[0]
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; SSSE3-NEXT: por %xmm4, %xmm0
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; SSSE3-NEXT: pshufb {{.*#+}} xmm1 = xmm1[0,1,2,3,4,5,6,7,8,9,10,11,12,13],zero,xmm1[15]
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; SSSE3-NEXT: pshufb {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm2[0],zero
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@ -253,26 +253,26 @@ define <4 x i64> @merge_4i64_i64_23zz(i64* %ptr) nounwind uwtable noinline ssp {
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define <8 x float> @merge_8f32_2f32_23z5(<2 x float>* %ptr) nounwind uwtable noinline ssp {
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; AVX1-LABEL: merge_8f32_2f32_23z5:
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; AVX1: # BB#0:
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; AVX1-NEXT: vmovupd 16(%rdi), %xmm0
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; AVX1-NEXT: vxorpd %xmm1, %xmm1, %xmm1
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; AVX1-NEXT: vmovhpd {{.*#+}} xmm1 = xmm1[0],mem[0]
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; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX1-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
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; AVX1-NEXT: vmovups 16(%rdi), %xmm1
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; AVX1-NEXT: vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: merge_8f32_2f32_23z5:
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; AVX2: # BB#0:
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; AVX2-NEXT: vmovupd 16(%rdi), %xmm0
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; AVX2-NEXT: vxorpd %xmm1, %xmm1, %xmm1
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; AVX2-NEXT: vmovhpd {{.*#+}} xmm1 = xmm1[0],mem[0]
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; AVX2-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX2-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
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; AVX2-NEXT: vmovdqu 16(%rdi), %xmm1
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; AVX2-NEXT: vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
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; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0
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; AVX2-NEXT: retq
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;
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; AVX512F-LABEL: merge_8f32_2f32_23z5:
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; AVX512F: # BB#0:
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; AVX512F-NEXT: vmovups 16(%rdi), %xmm0
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; AVX512F-NEXT: vxorps %xmm1, %xmm1, %xmm1
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; AVX512F-NEXT: vmovhpd {{.*#+}} xmm1 = xmm1[0],mem[0]
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; AVX512F-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX512F-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
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; AVX512F-NEXT: vmovdqu 16(%rdi), %xmm1
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; AVX512F-NEXT: vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
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; AVX512F-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0
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; AVX512F-NEXT: retq
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;
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; X32-AVX-LABEL: merge_8f32_2f32_23z5:
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@ -3241,8 +3241,7 @@ define <8 x i16> @cvt_4f32_to_8i16_zero(<4 x float> %a0) nounwind {
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; AVX512VL-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
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; AVX512VL-NEXT: vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,6,6,7]
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; AVX512VL-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,2]
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; AVX512VL-NEXT: vpxord %xmm1, %xmm1, %xmm1
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; AVX512VL-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
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; AVX512VL-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[8,9,10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero
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; AVX512VL-NEXT: addq $24, %rsp
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; AVX512VL-NEXT: popq %rbx
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; AVX512VL-NEXT: popq %r14
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@ -4149,8 +4148,7 @@ define void @store_cvt_4f32_to_8i16_zero(<4 x float> %a0, <8 x i16>* %a1) nounwi
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; AVX512VL-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
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; AVX512VL-NEXT: vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,6,6,7]
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; AVX512VL-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,2]
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; AVX512VL-NEXT: vpxord %xmm1, %xmm1, %xmm1
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; AVX512VL-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
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; AVX512VL-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[8,9,10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero
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; AVX512VL-NEXT: vmovdqa32 %xmm0, (%r14)
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; AVX512VL-NEXT: addq $16, %rsp
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; AVX512VL-NEXT: popq %rbx
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@ -5138,8 +5136,7 @@ define <8 x i16> @cvt_4f64_to_8i16_zero(<4 x double> %a0) nounwind {
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; AVX512VL-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
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; AVX512VL-NEXT: vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,6,6,7]
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; AVX512VL-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,2]
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; AVX512VL-NEXT: vpxord %xmm1, %xmm1, %xmm1
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; AVX512VL-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
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; AVX512VL-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[8,9,10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero
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; AVX512VL-NEXT: addq $40, %rsp
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; AVX512VL-NEXT: popq %rbx
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; AVX512VL-NEXT: popq %r14
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@ -5942,8 +5939,7 @@ define void @store_cvt_4f64_to_8i16_zero(<4 x double> %a0, <8 x i16>* %a1) nounw
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; AVX512VL-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
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; AVX512VL-NEXT: vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,6,6,7]
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; AVX512VL-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,2]
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; AVX512VL-NEXT: vpxord %xmm1, %xmm1, %xmm1
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; AVX512VL-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
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; AVX512VL-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[8,9,10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero
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; AVX512VL-NEXT: vmovdqa32 %xmm0, (%r14)
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; AVX512VL-NEXT: addq $32, %rsp
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; AVX512VL-NEXT: popq %rbx
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@ -622,7 +622,7 @@ define <32 x i8> @shuffle_v32i8_31_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_
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; AVX1-NEXT: vmovd %eax, %xmm2
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; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm2
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
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; AVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
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; AVX1-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
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; AVX1-NEXT: vpor %xmm0, %xmm2, %xmm0
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; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX1-NEXT: retq
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@ -280,7 +280,7 @@ define <8 x float> @combine_permps_as_permpd(<8 x float> %a) {
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define <32 x i8> @combine_pshufb_as_pslldq(<32 x i8> %a0) {
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; CHECK-LABEL: combine_pshufb_as_pslldq:
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; CHECK: # BB#0:
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; CHECK-NEXT: vpshufb {{.*#+}} ymm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm0[0,1,2,3,4,5],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm0[16,17,18,19,20,21]
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; CHECK-NEXT: vpslldq {{.*#+}} ymm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm0[0,1,2,3,4,5],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm0[16,17,18,19,20,21]
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; CHECK-NEXT: retq
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%res0 = call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %a0, <32 x i8> <i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5>)
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ret <32 x i8> %res0
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@ -289,7 +289,7 @@ define <32 x i8> @combine_pshufb_as_pslldq(<32 x i8> %a0) {
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define <32 x i8> @combine_pshufb_as_psrldq(<32 x i8> %a0) {
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; CHECK-LABEL: combine_pshufb_as_psrldq:
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; CHECK: # BB#0:
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; CHECK-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm0[31],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
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; CHECK-NEXT: vpsrldq {{.*#+}} ymm0 = ymm0[15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm0[31],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
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; CHECK-NEXT: retq
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%res0 = call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %a0, <32 x i8> <i8 15, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 15, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128>)
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ret <32 x i8> %res0
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@ -187,12 +187,12 @@ define <16 x i8> @combine_pshufb_psrldq(<16 x i8> %a0) {
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define <16 x i8> @combine_pshufb_as_pslldq(<16 x i8> %a0) {
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; SSE-LABEL: combine_pshufb_as_pslldq:
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; SSE: # BB#0:
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; SSE-NEXT: pshufb {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5]
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; SSE-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5]
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_pshufb_as_pslldq:
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; AVX: # BB#0:
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; AVX-NEXT: vpshufb {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5]
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; AVX-NEXT: vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5]
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; AVX-NEXT: retq
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%res0 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a0, <16 x i8> <i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5>)
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ret <16 x i8> %res0
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@ -201,12 +201,12 @@ define <16 x i8> @combine_pshufb_as_pslldq(<16 x i8> %a0) {
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define <16 x i8> @combine_pshufb_as_psrldq(<16 x i8> %a0) {
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; SSE-LABEL: combine_pshufb_as_psrldq:
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; SSE: # BB#0:
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; SSE-NEXT: pshufb {{.*#+}} xmm0 = xmm0[15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
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; SSE-NEXT: psrldq {{.*#+}} xmm0 = xmm0[15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_pshufb_as_psrldq:
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; AVX: # BB#0:
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; AVX-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
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; AVX-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
|
||||
; AVX-NEXT: retq
|
||||
%res0 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a0, <16 x i8> <i8 15, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128>)
|
||||
ret <16 x i8> %res0
|
||||
|
||||
@ -607,16 +607,14 @@ define <4 x i32> @combine_bitwise_ops_test3c(<4 x i32> %a, <4 x i32> %b, <4 x i3
|
||||
; SSE2: # BB#0:
|
||||
; SSE2-NEXT: pxor %xmm1, %xmm0
|
||||
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,2]
|
||||
; SSE2-NEXT: pxor %xmm1, %xmm1
|
||||
; SSE2-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
|
||||
; SSE2-NEXT: psrldq {{.*#+}} xmm0 = xmm0[8,9,10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero
|
||||
; SSE2-NEXT: retq
|
||||
;
|
||||
; SSSE3-LABEL: combine_bitwise_ops_test3c:
|
||||
; SSSE3: # BB#0:
|
||||
; SSSE3-NEXT: pxor %xmm1, %xmm0
|
||||
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,2]
|
||||
; SSSE3-NEXT: pxor %xmm1, %xmm1
|
||||
; SSSE3-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
|
||||
; SSSE3-NEXT: psrldq {{.*#+}} xmm0 = xmm0[8,9,10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero
|
||||
; SSSE3-NEXT: retq
|
||||
;
|
||||
; SSE41-LABEL: combine_bitwise_ops_test3c:
|
||||
@ -728,17 +726,15 @@ define <4 x i32> @combine_bitwise_ops_test6c(<4 x i32> %a, <4 x i32> %b, <4 x i3
|
||||
; SSE2-LABEL: combine_bitwise_ops_test6c:
|
||||
; SSE2: # BB#0:
|
||||
; SSE2-NEXT: pxor %xmm1, %xmm0
|
||||
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3]
|
||||
; SSE2-NEXT: pxor %xmm0, %xmm0
|
||||
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
|
||||
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,3,2,3]
|
||||
; SSE2-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
|
||||
; SSE2-NEXT: retq
|
||||
;
|
||||
; SSSE3-LABEL: combine_bitwise_ops_test6c:
|
||||
; SSSE3: # BB#0:
|
||||
; SSSE3-NEXT: pxor %xmm1, %xmm0
|
||||
; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3]
|
||||
; SSSE3-NEXT: pxor %xmm0, %xmm0
|
||||
; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
|
||||
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,3,2,3]
|
||||
; SSSE3-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
|
||||
; SSSE3-NEXT: retq
|
||||
;
|
||||
; SSE41-LABEL: combine_bitwise_ops_test6c:
|
||||
|
||||
@ -2068,10 +2068,10 @@ define <4 x i64> @shuf_zext_4i32_to_4i64_offset1(<4 x i32> %A) nounwind uwtable
|
||||
;
|
||||
; AVX1-LABEL: shuf_zext_4i32_to_4i64_offset1:
|
||||
; AVX1: # BB#0: # %entry
|
||||
; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm0[3],zero,zero,zero
|
||||
; AVX1-NEXT: vxorps %xmm2, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vblendps {{.*#+}} xmm0 = xmm2[0,1],xmm0[2],xmm2[3]
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
|
||||
; AVX1-NEXT: vxorps %xmm1, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vblendps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2],xmm1[3]
|
||||
; AVX1-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: shuf_zext_4i32_to_4i64_offset1:
|
||||
|
||||
Loading…
Reference in New Issue
Block a user