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[ARM] GlobalISel: Map shift operands to GPRs

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llvm-svn: 315067
This commit is contained in:
Diana Picus 2017-10-06 14:52:43 +00:00
parent af6f8e8c67
commit e8018ef17d
2 changed files with 85 additions and 0 deletions
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3
lib/Target/ARM/ARMRegisterBankInfo.cpp
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@ -218,6 +218,9 @@ ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
case G_AND:
case G_OR:
case G_XOR:
case G_LSHR:
case G_ASHR:
case G_SHL:
case G_SDIV:
case G_UDIV:
case G_SEXT:

82
test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
View File

@ -20,6 +20,10 @@
define void @test_or_s32() { ret void}
define void @test_xor_s32() { ret void}
define void @test_lshr_s32() { ret void }
define void @test_ashr_s32() { ret void }
define void @test_shl_s32() { ret void }
define void @test_loads() #0 { ret void }
define void @test_stores() #0 { ret void }
@ -505,6 +509,84 @@ body: |
%r0 = COPY %2(s32)
BX_RET 14, _, implicit %r0
...
---
name: test_lshr_s32
# CHECK-LABEL: name: test_lshr_s32
legalized: true
regBankSelected: false
selected: false
# CHECK: registers:
# CHECK: - { id: 0, class: gprb, preferred-register: '' }
# CHECK: - { id: 1, class: gprb, preferred-register: '' }
# CHECK: - { id: 2, class: gprb, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.0:
liveins: %r0, %r1
%0(s32) = COPY %r0
%1(s32) = COPY %r1
%2(s32) = G_LSHR %0, %1
%r0 = COPY %2(s32)
BX_RET 14, _, implicit %r0
...
---
name: test_ashr_s32
# CHECK-LABEL: name: test_ashr_s32
legalized: true
regBankSelected: false
selected: false
# CHECK: registers:
# CHECK: - { id: 0, class: gprb, preferred-register: '' }
# CHECK: - { id: 1, class: gprb, preferred-register: '' }
# CHECK: - { id: 2, class: gprb, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.0:
liveins: %r0, %r1
%0(s32) = COPY %r0
%1(s32) = COPY %r1
%2(s32) = G_ASHR %0, %1
%r0 = COPY %2(s32)
BX_RET 14, _, implicit %r0
...
---
name: test_shl_s32
# CHECK-LABEL: name: test_shl_s32
legalized: true
regBankSelected: false
selected: false
# CHECK: registers:
# CHECK: - { id: 0, class: gprb, preferred-register: '' }
# CHECK: - { id: 1, class: gprb, preferred-register: '' }
# CHECK: - { id: 2, class: gprb, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.0:
liveins: %r0, %r1
%0(s32) = COPY %r0
%1(s32) = COPY %r1
%2(s32) = G_SHL %0, %1
%r0 = COPY %2(s32)
BX_RET 14, _, implicit %r0
...
---
name: test_loads