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[X86][AVX-512] Allow EVEX encoded instruction selection when available for mul v8i32.

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Differential Revision: https://reviews.llvm.org/D32679

llvm-svn: 302127
This commit is contained in:
Igor Breger 2017-05-04 07:34:58 +00:00
parent cf8da85cba
commit e801f3e8fd
3 changed files with 8 additions and 3 deletions
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4
lib/Target/X86/X86InstrSSE.td
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@ -6727,14 +6727,14 @@ let Predicates = [HasAVX] in
loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>, loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
VEX_4V, VEX_WIG; VEX_4V, VEX_WIG;
let Predicates = [HasAVX2] in { let Predicates = [HasAVX2, NoVLX] in
defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256, defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
loadv4i64, i256mem, 0, SSE_PMULLD_ITINS>, loadv4i64, i256mem, 0, SSE_PMULLD_ITINS>,
VEX_4V, VEX_L, VEX_WIG; VEX_4V, VEX_L, VEX_WIG;
let Predicates = [HasAVX2] in
defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256, defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>, loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
VEX_4V, VEX_L, VEX_WIG; VEX_4V, VEX_L, VEX_WIG;
}
let Constraints = "$src1 = $dst" in { let Constraints = "$src1 = $dst" in {
defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128, defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,

5
test/CodeGen/X86/avx-isa-check.ll
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@ -680,3 +680,8 @@ define <4 x double> @_inreg4xdouble(double %a) {
%c = shufflevector <4 x double> %b, <4 x double> undef, <4 x i32> zeroinitializer %c = shufflevector <4 x double> %b, <4 x double> undef, <4 x i32> zeroinitializer
ret <4 x double> %c ret <4 x double> %c
} }
define <8 x i32> @test_mul_v8i32(<8 x i32> %arg1, <8 x i32> %arg2) #0 {
%ret = mul <8 x i32> %arg1, %arg2
ret <8 x i32> %ret
}

2
test/CodeGen/X86/avx512vl-arith.ll
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@ -176,7 +176,7 @@ define <8 x i32> @vpsubd256_test(<8 x i32> %i, <8 x i32> %j) nounwind readnone {
define <8 x i32> @vpmulld256_test(<8 x i32> %i, <8 x i32> %j) { define <8 x i32> @vpmulld256_test(<8 x i32> %i, <8 x i32> %j) {
; CHECK-LABEL: vpmulld256_test: ; CHECK-LABEL: vpmulld256_test:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: vpmulld %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x40,0xc1] ; CHECK-NEXT: vpmulld %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x40,0xc1]
; CHECK-NEXT: retq ## encoding: [0xc3] ; CHECK-NEXT: retq ## encoding: [0xc3]
%x = mul <8 x i32> %i, %j %x = mul <8 x i32> %i, %j
ret <8 x i32> %x ret <8 x i32> %x