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[X86][AVX-512] Allow EVEX encoded instruction selection when available for mul v8i32.
Differential Revision: https://reviews.llvm.org/D32679 llvm-svn: 302127
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@ -6727,14 +6727,14 @@ let Predicates = [HasAVX] in
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loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
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VEX_4V, VEX_WIG;
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let Predicates = [HasAVX2] in {
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let Predicates = [HasAVX2, NoVLX] in
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defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
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loadv4i64, i256mem, 0, SSE_PMULLD_ITINS>,
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VEX_4V, VEX_L, VEX_WIG;
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let Predicates = [HasAVX2] in
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defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
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loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
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VEX_4V, VEX_L, VEX_WIG;
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}
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let Constraints = "$src1 = $dst" in {
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defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
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@ -680,3 +680,8 @@ define <4 x double> @_inreg4xdouble(double %a) {
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%c = shufflevector <4 x double> %b, <4 x double> undef, <4 x i32> zeroinitializer
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ret <4 x double> %c
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}
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define <8 x i32> @test_mul_v8i32(<8 x i32> %arg1, <8 x i32> %arg2) #0 {
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%ret = mul <8 x i32> %arg1, %arg2
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ret <8 x i32> %ret
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}
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@ -176,7 +176,7 @@ define <8 x i32> @vpsubd256_test(<8 x i32> %i, <8 x i32> %j) nounwind readnone {
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define <8 x i32> @vpmulld256_test(<8 x i32> %i, <8 x i32> %j) {
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; CHECK-LABEL: vpmulld256_test:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpmulld %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x40,0xc1]
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; CHECK-NEXT: vpmulld %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x40,0xc1]
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; CHECK-NEXT: retq ## encoding: [0xc3]
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%x = mul <8 x i32> %i, %j
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ret <8 x i32> %x
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