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Add check for completeness. Note that this doesn't actually have any
effect with the way the current code is structured. llvm-svn: 79792
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@ -3460,7 +3460,7 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
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unsigned EVTBits = ExtVT.getSizeInBits();
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unsigned ShAmt = 0;
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if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
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if (N0.getOpcode() == ISD::SRL && N0.hasOneUse() && ExtVT.isRound()) {
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if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
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ShAmt = N01->getZExtValue();
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// Is the shift amount a multiple of size of VT?
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