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[Tablegen][SubtargetEmitter] Improve expansion of predicates of a variant scheduling class.

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This patch refactors the logic that expands predicates of a variant scheduling
class.

The idea is to improve the readability of the auto-generated code by removing
redundant parentheses around predicate expressions, and by removing redundant
if(true) statements.

This patch replaces the definition of NoSchedPred in TargetSchedule.td with an
instance of MCSchedPredicate. The new definition is sematically equivalent to
the previous one. The main difference is that now SubtargetEmitter knows that it
represents predicate "true".

Before this patch, we always generated an if (true) for the default transition
of a variant scheduling class.

Example (taken from AArch64GenSubtargetInfo.inc) :

```
if (SchedModel->getProcessorID() == 3) { // CycloneModel
  if ((TII->isScaledAddr(*MI)))
    return 927; // (WriteIS_WriteLD)_ReadBaseRS
  if ((true))
    return 928; // WriteLD_ReadDefault
}
```

Extra parentheses were also generated around the predicate expressions.

With this patch, we get the following auto-generated checks:

```
if (SchedModel->getProcessorID() == 3) { // CycloneModel
  if (TII->isScaledAddr(*MI))
    return 927; // (WriteIS_WriteLD)_ReadBaseRS
  return 928; // WriteLD_ReadDefault
}
```

The new auto-generated code behaves exactly the same as before. So, technically
this is a non functional change.

Differential revision: https://reviews.llvm.org/D50566

llvm-svn: 339552
This commit is contained in:
Andrea Di Biagio 2018-08-13 11:09:04 +00:00
parent 6556afe480
commit e84b02f47e
2 changed files with 40 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
include/llvm/Target/TargetSchedule.td
View File

@ -373,7 +373,7 @@ class SchedPredicate<code pred> : SchedPredicateBase {
SchedMachineModel SchedModel = ?;
code Predicate = pred;
}
def NoSchedPred : SchedPredicate<[{true}]>;
def NoSchedPred : MCSchedPredicate<TruePred>;
// Associate a predicate with a list of SchedReadWrites. By default,
// the selected SchedReadWrites are still associated with a single

54
utils/TableGen/SubtargetEmitter.cpp
View File

@ -1480,30 +1480,54 @@ static void emitPredicateProlog(const RecordKeeper &Records, raw_ostream &OS) {
}
static void emitPredicates(const CodeGenSchedTransition &T,
const CodeGenSchedClass &SC,
PredicateExpander &PE,
const CodeGenSchedClass &SC, PredicateExpander &PE,
raw_ostream &OS) {
std::string Buffer;
raw_string_ostream StringStream(Buffer);
formatted_raw_ostream FOS(StringStream);
FOS.PadToColumn(6);
FOS << "if (";
for (RecIter RI = T.PredTerm.begin(), RE = T.PredTerm.end(); RI != RE; ++RI) {
if (RI != T.PredTerm.begin()) {
FOS << "\n";
FOS.PadToColumn(8);
FOS << "&& ";
auto IsTruePredicate = [](const Record *Rec) {
return Rec->isSubClassOf("MCSchedPredicate") &&
Rec->getValueAsDef("Pred")->isSubClassOf("MCTrue");
};
// If not all predicates are MCTrue, then we need an if-stmt.
unsigned NumNonTruePreds =
T.PredTerm.size() - count_if(T.PredTerm, IsTruePredicate);
if (NumNonTruePreds) {
bool FirstNonTruePredicate = true;
for (const Record *Rec : T.PredTerm) {
// Skip predicates that evaluate to "true".
if (IsTruePredicate(Rec))
continue;
if (FirstNonTruePredicate) {
FOS << "if (";
FirstNonTruePredicate = false;
} else {
FOS << "\n";
FOS.PadToColumn(8);
FOS << "&& ";
}
if (Rec->isSubClassOf("MCSchedPredicate")) {
PE.expandPredicate(FOS, Rec->getValueAsDef("Pred"));
continue;
}
// Expand this legacy predicate and wrap it around braces if there is more
// than one predicate to expand.
FOS << ((NumNonTruePreds > 1) ? "(" : "")
<< Rec->getValueAsString("Predicate")
<< ((NumNonTruePreds > 1) ? ")" : "");
}
const Record *Rec = *RI;
if (Rec->isSubClassOf("MCSchedPredicate"))
PE.expandPredicate(FOS, Rec->getValueAsDef("Pred"));
else
FOS << "(" << Rec->getValueAsString("Predicate") << ")";
FOS << ")\n"; // end of if-stmt
FOS.PadToColumn(8);
}
FOS << ")\n";
FOS.PadToColumn(8);
FOS << "return " << T.ToClassIdx << "; // " << SC.Name << '\n';
FOS.flush();
OS << Buffer;