1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 11:13:28 +01:00

Fix typos

llvm-svn: 209982
This commit is contained in:
Alp Toker 2014-05-31 21:26:28 +00:00
parent c6984bfa5e
commit e8634eb077
4 changed files with 5 additions and 5 deletions

View File

@ -1382,7 +1382,7 @@ DIE *DwarfUnit::getOrCreateSubprogramDIE(DISubprogram SP) {
if (DISubprogram SPDecl = SP.getFunctionDeclaration()) {
// Add subprogram definitions to the CU die directly.
ContextDIE = &getUnitDie();
// Build the decl now to ensure it preceeds the definition.
// Build the decl now to ensure it precedes the definition.
getOrCreateSubprogramDIE(SPDecl);
}

View File

@ -744,7 +744,7 @@ bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
.Default("");
#if defined(__aarch64__)
// We need to check crypto seperately since we need all of the crypto
// We need to check crypto separately since we need all of the crypto
// extensions to enable the subtarget feature
if (CPUFeatures[I] == "aes")
crypto |= CAP_AES;

View File

@ -148,9 +148,9 @@ def : ReadAdvance<ReadVLD, 0>;
// ALU - Most operands in the ALU pipes are not needed for two cycles. Shiftable
// operands are needed one cycle later if and only if they are to be
// shifted. Otherwise, they too are needed two cycle later. This same
// shifted. Otherwise, they too are needed two cycles later. This same
// ReadAdvance applies to Extended registers as well, even though there is
// a seperate SchedPredicate for them.
// a separate SchedPredicate for them.
def : ReadAdvance<ReadI, 2, [WriteImm,WriteI,
WriteISReg, WriteIEReg,WriteIS,
WriteID32,WriteID64,

View File

@ -7,7 +7,7 @@
; CHECK: DW_TAG_subprogram
; CHECK: DW_AT_abstract_origin {{.*}}{[[ABS:.*]]}
; FIXME: An out of line definition preceeding an inline usage doesn't properly
; FIXME: An out of line definition preceding an inline usage doesn't properly
; reference abstract variables.
; CHECK: DW_TAG_formal_parameter
; CHECK-NEXT: DW_AT_name {{.*}} "sp"