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Reapply [ValueTracking] Support min/max selects in computeConstantRange()
Add support for min/max flavor selects in computeConstantRange(), which allows us to fold comparisons of a min/max against a constant in InstSimplify. This fixes an infinite InstCombine loop, with the test case taken from D59378. Relative to the previous iteration, this contains some adjustments for AMDGPU med3 tests: The AMDGPU target runs InstSimplify prior to codegen, which ends up constant folding some existing med3 tests after this change. To preserve these tests a hidden -amdgpu-scalar-ir-passes option is added, which allows disabling scalar IR passes (that use InstSimplify) for testing purposes. Differential Revision: https://reviews.llvm.org/D59506 llvm-svn: 357870
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@ -5689,7 +5689,28 @@ static void setLimitsForSelectPattern(const SelectInst &SI, APInt &Lower,
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return;
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return;
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}
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}
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// TODO Handle min/max flavors.
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const APInt *C;
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if (!match(LHS, m_APInt(C)) && !match(RHS, m_APInt(C)))
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return;
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switch (R.Flavor) {
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case SPF_UMIN:
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Upper = *C + 1;
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break;
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case SPF_UMAX:
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Lower = *C;
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break;
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case SPF_SMIN:
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Lower = APInt::getSignedMinValue(BitWidth);
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Upper = *C + 1;
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break;
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case SPF_SMAX:
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Lower = *C;
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Upper = APInt::getSignedMaxValue(BitWidth) + 1;
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break;
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default:
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break;
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}
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}
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}
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ConstantRange llvm::computeConstantRange(const Value *V, bool UseInstrInfo) {
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ConstantRange llvm::computeConstantRange(const Value *V, bool UseInstrInfo) {
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@ -169,6 +169,12 @@ EnableDCEInRA("amdgpu-dce-in-ra",
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cl::init(true), cl::Hidden,
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cl::init(true), cl::Hidden,
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cl::desc("Enable machine DCE inside regalloc"));
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cl::desc("Enable machine DCE inside regalloc"));
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static cl::opt<bool> EnableScalarIRPasses(
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"amdgpu-scalar-ir-passes",
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cl::desc("Enable scalar IR passes"),
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cl::init(true),
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cl::Hidden);
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extern "C" void LLVMInitializeAMDGPUTarget() {
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extern "C" void LLVMInitializeAMDGPUTarget() {
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// Register the target
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// Register the target
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RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
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RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
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@ -670,7 +676,8 @@ void AMDGPUPassConfig::addIRPasses() {
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if (EnableSROA)
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if (EnableSROA)
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addPass(createSROAPass());
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addPass(createSROAPass());
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addStraightLineScalarOptimizationPasses();
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if (EnableScalarIRPasses)
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addStraightLineScalarOptimizationPasses();
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if (EnableAMDGPUAliasAnalysis) {
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if (EnableAMDGPUAliasAnalysis) {
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addPass(createAMDGPUAAWrapperPass());
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addPass(createAMDGPUAAWrapperPass());
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@ -696,7 +703,7 @@ void AMDGPUPassConfig::addIRPasses() {
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// %1 = shl %a, 2
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// %1 = shl %a, 2
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//
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//
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// but EarlyCSE can do neither of them.
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// but EarlyCSE can do neither of them.
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if (getOptLevel() != CodeGenOpt::None)
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if (getOptLevel() != CodeGenOpt::None && EnableScalarIRPasses)
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addEarlyCSEOrGVNPass();
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addEarlyCSEOrGVNPass();
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}
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}
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48
test/CodeGen/AMDGPU/med3-no-simplify.ll
Normal file
48
test/CodeGen/AMDGPU/med3-no-simplify.ll
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@ -0,0 +1,48 @@
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; RUN: llc -march=amdgcn -verify-machineinstrs -amdgpu-scalar-ir-passes=false < %s | FileCheck -check-prefix=GCN -check-prefix=SICIVI -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -amdgpu-scalar-ir-passes=false < %s | FileCheck -check-prefix=GCN -check-prefix=SICIVI -check-prefix=VI %s
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; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs -amdgpu-scalar-ir-passes=false < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s
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; These tests are split out from umed3.ll and smed3.ll and use the
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; -amdgpu-scalar-ir-passes=false flag, because InstSimplify would constant
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; fold these functions otherwise.
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declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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; GCN-LABEL: {{^}}v_test_umed3_r_i_i_constant_order_i32:
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; GCN: v_max_u32_e32 v{{[0-9]+}}, 17, v{{[0-9]+}}
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; GCN: v_min_u32_e32 v{{[0-9]+}}, 12, v{{[0-9]+}}
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define amdgpu_kernel void @v_test_umed3_r_i_i_constant_order_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) #1 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
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%outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
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%a = load i32, i32 addrspace(1)* %gep0
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%icmp0 = icmp ugt i32 %a, 17
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%i0 = select i1 %icmp0, i32 %a, i32 17
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%icmp1 = icmp ult i32 %i0, 12
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%i1 = select i1 %icmp1, i32 %i0, i32 12
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store i32 %i1, i32 addrspace(1)* %outgep
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ret void
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}
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; GCN-LABEL: {{^}}v_test_smed3_r_i_i_constant_order_i32:
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; GCN: v_max_i32_e32 v{{[0-9]+}}, 17, v{{[0-9]+}}
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; GCN: v_min_i32_e32 v{{[0-9]+}}, 12, v{{[0-9]+}}
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define amdgpu_kernel void @v_test_smed3_r_i_i_constant_order_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) #1 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
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%outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
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%a = load i32, i32 addrspace(1)* %gep0
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%icmp0 = icmp sgt i32 %a, 17
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%i0 = select i1 %icmp0, i32 %a, i32 17
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%icmp1 = icmp slt i32 %i0, 12
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%i1 = select i1 %icmp1, i32 %i0, i32 12
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store i32 %i1, i32 addrspace(1)* %outgep
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ret void
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}
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@ -42,25 +42,6 @@ define amdgpu_kernel void @v_test_smed3_multi_use_r_i_i_i32(i32 addrspace(1)* %o
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ret void
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ret void
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}
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}
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; GCN-LABEL: {{^}}v_test_smed3_r_i_i_constant_order_i32:
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; GCN: v_max_i32_e32 v{{[0-9]+}}, 17, v{{[0-9]+}}
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; GCN: v_min_i32_e32 v{{[0-9]+}}, 12, v{{[0-9]+}}
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define amdgpu_kernel void @v_test_smed3_r_i_i_constant_order_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) #1 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
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%outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
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%a = load i32, i32 addrspace(1)* %gep0
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%icmp0 = icmp sgt i32 %a, 17
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%i0 = select i1 %icmp0, i32 %a, i32 17
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%icmp1 = icmp slt i32 %i0, 12
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%i1 = select i1 %icmp1, i32 %i0, i32 12
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store i32 %i1, i32 addrspace(1)* %outgep
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ret void
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}
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; GCN-LABEL: {{^}}v_test_smed3_r_i_i_sign_mismatch_i32:
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; GCN-LABEL: {{^}}v_test_smed3_r_i_i_sign_mismatch_i32:
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; GCN: v_max_u32_e32 v{{[0-9]+}}, 12, v{{[0-9]+}}
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; GCN: v_max_u32_e32 v{{[0-9]+}}, 12, v{{[0-9]+}}
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; GCN: v_min_i32_e32 v{{[0-9]+}}, 17, v{{[0-9]+}}
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; GCN: v_min_i32_e32 v{{[0-9]+}}, 17, v{{[0-9]+}}
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@ -42,25 +42,6 @@ define amdgpu_kernel void @v_test_umed3_multi_use_r_i_i_i32(i32 addrspace(1)* %o
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ret void
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ret void
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}
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}
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; GCN-LABEL: {{^}}v_test_umed3_r_i_i_constant_order_i32:
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; GCN: v_max_u32_e32 v{{[0-9]+}}, 17, v{{[0-9]+}}
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; GCN: v_min_u32_e32 v{{[0-9]+}}, 12, v{{[0-9]+}}
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define amdgpu_kernel void @v_test_umed3_r_i_i_constant_order_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) #1 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
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%outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
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%a = load i32, i32 addrspace(1)* %gep0
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%icmp0 = icmp ugt i32 %a, 17
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%i0 = select i1 %icmp0, i32 %a, i32 17
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%icmp1 = icmp ult i32 %i0, 12
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%i1 = select i1 %icmp1, i32 %i0, i32 12
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store i32 %i1, i32 addrspace(1)* %outgep
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ret void
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}
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; GCN-LABEL: {{^}}v_test_umed3_r_i_i_sign_mismatch_i32:
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; GCN-LABEL: {{^}}v_test_umed3_r_i_i_sign_mismatch_i32:
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; GCN: v_max_i32_e32 v{{[0-9]+}}, 12, v{{[0-9]+}}
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; GCN: v_max_i32_e32 v{{[0-9]+}}, 12, v{{[0-9]+}}
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; GCN: v_min_u32_e32 v{{[0-9]+}}, 17, v{{[0-9]+}}
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; GCN: v_min_u32_e32 v{{[0-9]+}}, 17, v{{[0-9]+}}
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ret i32 %res
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ret i32 %res
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}
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}
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; Check that there is no infinite loop because of reverse cmp transformation:
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; (icmp slt smax(PositiveA, B) 2) -> (icmp eq B 1)
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define i32 @clamp_check_for_no_infinite_loop3(i32 %i) {
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; CHECK-LABEL: @clamp_check_for_no_infinite_loop3(
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; CHECK-NEXT: [[I2:%.*]] = icmp sgt i32 [[I:%.*]], 1
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; CHECK-NEXT: [[I3:%.*]] = select i1 [[I2]], i32 [[I]], i32 1
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; CHECK-NEXT: br i1 true, label [[TRUELABEL:%.*]], label [[FALSELABEL:%.*]]
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; CHECK: truelabel:
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; CHECK-NEXT: [[I5:%.*]] = icmp slt i32 [[I3]], 2
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; CHECK-NEXT: [[I6:%.*]] = select i1 [[I5]], i32 [[I3]], i32 2
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; CHECK-NEXT: [[I7:%.*]] = shl nuw nsw i32 [[I6]], 2
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; CHECK-NEXT: ret i32 [[I7]]
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; CHECK: falselabel:
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; CHECK-NEXT: ret i32 0
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;
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%i2 = icmp sgt i32 %i, 1
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%i3 = select i1 %i2, i32 %i, i32 1
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%i4 = icmp sgt i32 %i3, 0
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br i1 %i4, label %truelabel, label %falselabel
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truelabel: ; %i<=1, %i3>0
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%i5 = icmp slt i32 %i3, 2
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%i6 = select i1 %i5, i32 %i3, i32 2
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%i7 = shl nuw nsw i32 %i6, 2
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ret i32 %i7
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falselabel:
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ret i32 0
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}
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; The next 3 min tests should canonicalize to the same form...and not infinite loop.
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; The next 3 min tests should canonicalize to the same form...and not infinite loop.
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define double @PR31751_umin1(i32 %x) {
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define double @PR31751_umin1(i32 %x) {
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@ -1213,7 +1213,7 @@ define i32 @test66(i32 %x) {
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; CHECK-LABEL: @test66(
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; CHECK-LABEL: @test66(
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; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[X:%.*]], -101
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; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[X:%.*]], -101
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; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[X]], i32 -101
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; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[X]], i32 -101
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; CHECK-NEXT: [[RES:%.*]] = add i32 [[TMP2]], 1
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; CHECK-NEXT: [[RES:%.*]] = add nuw i32 [[TMP2]], 1
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; CHECK-NEXT: ret i32 [[RES]]
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; CHECK-NEXT: ret i32 [[RES]]
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;
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;
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%1 = xor i32 %x, -1
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%1 = xor i32 %x, -1
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@ -3,10 +3,7 @@
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define i1 @test_umax1(i32 %n) {
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define i1 @test_umax1(i32 %n) {
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; CHECK-LABEL: @test_umax1(
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; CHECK-LABEL: @test_umax1(
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; CHECK-NEXT: [[C1:%.*]] = icmp ugt i32 [[N:%.*]], 10
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; CHECK-NEXT: ret i1 true
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; CHECK-NEXT: [[S:%.*]] = select i1 [[C1]], i32 [[N]], i32 10
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; CHECK-NEXT: [[C2:%.*]] = icmp ugt i32 [[S]], 9
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; CHECK-NEXT: ret i1 [[C2]]
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;
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;
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%c1 = icmp ugt i32 %n, 10
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%c1 = icmp ugt i32 %n, 10
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%s = select i1 %c1, i32 %n, i32 10
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%s = select i1 %c1, i32 %n, i32 10
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@ -40,10 +37,7 @@ define i1 @test_umax3(i32 %n) {
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define i1 @test_umin1(i32 %n) {
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define i1 @test_umin1(i32 %n) {
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; CHECK-LABEL: @test_umin1(
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; CHECK-LABEL: @test_umin1(
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; CHECK-NEXT: [[C1:%.*]] = icmp ult i32 [[N:%.*]], 10
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; CHECK-NEXT: ret i1 true
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; CHECK-NEXT: [[S:%.*]] = select i1 [[C1]], i32 [[N]], i32 10
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; CHECK-NEXT: [[C2:%.*]] = icmp ult i32 [[S]], 11
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; CHECK-NEXT: ret i1 [[C2]]
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;
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;
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%c1 = icmp ult i32 %n, 10
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%c1 = icmp ult i32 %n, 10
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%s = select i1 %c1, i32 %n, i32 10
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%s = select i1 %c1, i32 %n, i32 10
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@ -77,10 +71,7 @@ define i1 @test_umin3(i32 %n) {
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define i1 @test_smax1(i32 %n) {
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define i1 @test_smax1(i32 %n) {
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; CHECK-LABEL: @test_smax1(
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; CHECK-LABEL: @test_smax1(
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; CHECK-NEXT: [[C1:%.*]] = icmp sgt i32 [[N:%.*]], -10
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; CHECK-NEXT: ret i1 true
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; CHECK-NEXT: [[S:%.*]] = select i1 [[C1]], i32 [[N]], i32 -10
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; CHECK-NEXT: [[C2:%.*]] = icmp sgt i32 [[S]], -11
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; CHECK-NEXT: ret i1 [[C2]]
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;
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;
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%c1 = icmp sgt i32 %n, -10
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%c1 = icmp sgt i32 %n, -10
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%s = select i1 %c1, i32 %n, i32 -10
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%s = select i1 %c1, i32 %n, i32 -10
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@ -114,10 +105,7 @@ define i1 @test_smax3(i32 %n) {
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define i1 @test_smin1(i32 %n) {
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define i1 @test_smin1(i32 %n) {
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; CHECK-LABEL: @test_smin1(
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; CHECK-LABEL: @test_smin1(
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; CHECK-NEXT: [[C1:%.*]] = icmp slt i32 [[N:%.*]], 10
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; CHECK-NEXT: ret i1 true
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; CHECK-NEXT: [[S:%.*]] = select i1 [[C1]], i32 [[N]], i32 10
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; CHECK-NEXT: [[C2:%.*]] = icmp slt i32 [[S]], 11
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; CHECK-NEXT: ret i1 [[C2]]
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;
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;
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%c1 = icmp slt i32 %n, 10
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%c1 = icmp slt i32 %n, 10
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%s = select i1 %c1, i32 %n, i32 10
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%s = select i1 %c1, i32 %n, i32 10
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