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[InstCombine] use m_APInt to allow icmp X, C folds for splat constant vectors
Of course, we really need to refactor and fix all of the cmp predicates, but this one is interesting because without it, we later perform an information-losing transform of icmp (shl 1, Y), C, and we can't recover the better fold. llvm-svn: 279263
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@ -3622,25 +3622,30 @@ Instruction *InstCombiner::visitICmpInst(ICmpInst &I) {
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Constant::getAllOnesValue(Op0->getType()));
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}
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break;
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case ICmpInst::ICMP_UGT:
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case ICmpInst::ICMP_UGT: {
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if (Op0Min.ugt(Op1Max)) // A >u B -> true if min(A) > max(B)
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return replaceInstUsesWith(I, ConstantInt::getTrue(I.getType()));
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if (Op0Max.ule(Op1Min)) // A >u B -> false if max(A) <= max(B)
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return replaceInstUsesWith(I, ConstantInt::getFalse(I.getType()));
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if (Op1Max == Op0Min) // A >u B -> A != B if min(A) == max(B)
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return new ICmpInst(ICmpInst::ICMP_NE, Op0, Op1);
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if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
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if (Op1Min == Op0Max-1) // A >u C -> A == C+1 if max(a)-1 == C
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const APInt *CmpC;
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if (match(Op1, m_APInt(CmpC))) {
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// A >u C -> A == C+1 if max(a)-1 == C
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if (*CmpC == Op0Max - 1)
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return new ICmpInst(ICmpInst::ICMP_EQ, Op0,
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Builder->getInt(CI->getValue()+1));
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ConstantInt::get(Op1->getType(), *CmpC + 1));
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// (x >u 2147483647) -> (x <s 0) -> true if sign bit set
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if (CI->isMaxValue(true))
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if (CmpC->isMaxSignedValue())
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return new ICmpInst(ICmpInst::ICMP_SLT, Op0,
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Constant::getNullValue(Op0->getType()));
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}
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break;
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}
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case ICmpInst::ICMP_SLT:
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if (Op0Max.slt(Op1Min)) // A <s B -> true if max(A) < min(C)
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return replaceInstUsesWith(I, ConstantInt::getTrue(I.getType()));
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@ -1672,7 +1672,7 @@ define i1 @icmp_shl_1_V_uge_2147483648(i32 %V) {
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define <2 x i1> @icmp_shl_1_V_uge_2147483648_vec(<2 x i32> %V) {
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; CHECK-LABEL: @icmp_shl_1_V_uge_2147483648_vec(
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; CHECK-NEXT: [[SHL:%.*]] = shl <2 x i32> <i32 1, i32 1>, %V
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; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i32> [[SHL]], <i32 2147483647, i32 2147483647>
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; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i32> [[SHL]], zeroinitializer
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; CHECK-NEXT: ret <2 x i1> [[CMP]]
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;
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%shl = shl <2 x i32> <i32 1, i32 1>, %V
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@ -2591,6 +2591,10 @@ define i1 @ugtMaxSignedVal(i8 %a) {
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}
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define <2 x i1> @ugtMaxSignedValVec(<2 x i8> %a) {
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; CHECK-LABEL: @ugtMaxSignedValVec(
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; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i8> %a, zeroinitializer
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; CHECK-NEXT: ret <2 x i1> [[CMP]]
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;
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%cmp = icmp ugt <2 x i8> %a, <i8 127, i8 127>
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ret <2 x i1> %cmp
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}
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@ -2609,7 +2613,7 @@ define i1 @ugtKnownBits(i8 %a) {
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define <2 x i1> @ugtKnownBitsVec(<2 x i8> %a) {
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; CHECK-LABEL: @ugtKnownBitsVec(
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; CHECK-NEXT: [[B:%.*]] = and <2 x i8> %a, <i8 17, i8 17>
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; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i8> [[B]], <i8 16, i8 16>
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i8> [[B]], <i8 17, i8 17>
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; CHECK-NEXT: ret <2 x i1> [[CMP]]
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;
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%b = and <2 x i8> %a, <i8 17, i8 17>
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