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[DAGTypeLegalizer] Handle SIGN/ZERO_EXTEND in WidenVecRes_Convert().

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In case of a SIGN/ZERO_EXTEND of an incomplete vector type (using only a
partial number of available vector elements), WidenVecRes_Convert() used to
resort to scalarization.

This patch adds a handling of the (common) case where an input vector can be
found of same width as the widened result vector, by converting the node to
SIGN/ZERO_EXTEND_VECTOR_INREG.

Review: Eli Friedman
llvm-svn: 293268
This commit is contained in:
Jonas Paulsson 2017-01-27 07:46:26 +00:00
parent 048d1de98a
commit e87466a278
3 changed files with 191 additions and 0 deletions
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9
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
View File

@ -2326,6 +2326,15 @@ SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
return DAG.getNode(Opcode, DL, WidenVT, InOp);
return DAG.getNode(Opcode, DL, WidenVT, InOp, N->getOperand(1), Flags);
}
if (WidenVT.getSizeInBits() == InVT.getSizeInBits()) {
// If both input and result vector types are of same width, extend
// operations should be done with SIGN/ZERO_EXTEND_VECTOR_INREG, which
// accepts fewer elements in the result than in the input.
if (Opcode == ISD::SIGN_EXTEND)
return DAG.getSignExtendVectorInReg(InOp, DL, WidenVT);
if (Opcode == ISD::ZERO_EXTEND)
return DAG.getZeroExtendVectorInReg(InOp, DL, WidenVT);
}
}
if (TLI.isTypeLegal(InWidenVT)) {

91
test/CodeGen/SystemZ/vec-sext.ll Normal file
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@ -0,0 +1,91 @@
; Test that vector sexts are done efficently with unpack instructions also in
; case of fewer elements than allowed, e.g. <2 x i32>.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
define <2 x i16> @fun1(<2 x i8> %val1) {
; CHECK-LABEL: fun1:
; CHECK: vuphb %v24, %v24
; CHECK-NEXT: br %r14
%z = sext <2 x i8> %val1 to <2 x i16>
ret <2 x i16> %z
}
define <2 x i32> @fun2(<2 x i8> %val1) {
; CHECK-LABEL: fun2:
; CHECK: vuphb %v0, %v24
; CHECK-NEXT: vuphh %v24, %v0
; CHECK-NEXT: br %r14
%z = sext <2 x i8> %val1 to <2 x i32>
ret <2 x i32> %z
}
define <2 x i64> @fun3(<2 x i8> %val1) {
; CHECK-LABEL: fun3:
; CHECK: vuphb %v0, %v24
; CHECK-NEXT: vuphh %v0, %v0
; CHECK-NEXT: vuphf %v24, %v0
; CHECK-NEXT: br %r14
%z = sext <2 x i8> %val1 to <2 x i64>
ret <2 x i64> %z
}
define <2 x i32> @fun4(<2 x i16> %val1) {
; CHECK-LABEL: fun4:
; CHECK: vuphh %v24, %v24
; CHECK-NEXT: br %r14
%z = sext <2 x i16> %val1 to <2 x i32>
ret <2 x i32> %z
}
define <2 x i64> @fun5(<2 x i16> %val1) {
; CHECK-LABEL: fun5:
; CHECK: vuphh %v0, %v24
; CHECK-NEXT: vuphf %v24, %v0
; CHECK-NEXT: br %r14
%z = sext <2 x i16> %val1 to <2 x i64>
ret <2 x i64> %z
}
define <2 x i64> @fun6(<2 x i32> %val1) {
; CHECK-LABEL: fun6:
; CHECK: vuphf %v24, %v24
; CHECK-NEXT: br %r14
%z = sext <2 x i32> %val1 to <2 x i64>
ret <2 x i64> %z
}
define <4 x i16> @fun7(<4 x i8> %val1) {
; CHECK-LABEL: fun7:
; CHECK: vuphb %v24, %v24
; CHECK-NEXT: br %r14
%z = sext <4 x i8> %val1 to <4 x i16>
ret <4 x i16> %z
}
define <4 x i32> @fun8(<4 x i8> %val1) {
; CHECK-LABEL: fun8:
; CHECK: vuphb %v0, %v24
; CHECK-NEXT: vuphh %v24, %v0
; CHECK-NEXT: br %r14
%z = sext <4 x i8> %val1 to <4 x i32>
ret <4 x i32> %z
}
define <4 x i32> @fun9(<4 x i16> %val1) {
; CHECK-LABEL: fun9:
; CHECK: vuphh %v24, %v24
; CHECK-NEXT: br %r14
%z = sext <4 x i16> %val1 to <4 x i32>
ret <4 x i32> %z
}
define <8 x i16> @fun10(<8 x i8> %val1) {
; CHECK-LABEL: fun10:
; CHECK: vuphb %v24, %v24
; CHECK-NEXT: br %r14
%z = sext <8 x i8> %val1 to <8 x i16>
ret <8 x i16> %z
}

91
test/CodeGen/SystemZ/vec-zext.ll Normal file
View File

@ -0,0 +1,91 @@
; Test that vector zexts are done efficently with unpack instructions also in
; case of fewer elements than allowed, e.g. <2 x i32>.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
define <2 x i16> @fun1(<2 x i8> %val1) {
; CHECK-LABEL: fun1:
; CHECK: vuplhb %v24, %v24
; CHECK-NEXT: br %r14
%z = zext <2 x i8> %val1 to <2 x i16>
ret <2 x i16> %z
}
define <2 x i32> @fun2(<2 x i8> %val1) {
; CHECK-LABEL: fun2:
; CHECK: vuplhb %v0, %v24
; CHECK-NEXT: vuplhh %v24, %v0
; CHECK-NEXT: br %r14
%z = zext <2 x i8> %val1 to <2 x i32>
ret <2 x i32> %z
}
define <2 x i64> @fun3(<2 x i8> %val1) {
; CHECK-LABEL: fun3:
; CHECK: vuplhb %v0, %v24
; CHECK-NEXT: vuplhh %v0, %v0
; CHECK-NEXT: vuplhf %v24, %v0
; CHECK-NEXT: br %r14
%z = zext <2 x i8> %val1 to <2 x i64>
ret <2 x i64> %z
}
define <2 x i32> @fun4(<2 x i16> %val1) {
; CHECK-LABEL: fun4:
; CHECK: vuplhh %v24, %v24
; CHECK-NEXT: br %r14
%z = zext <2 x i16> %val1 to <2 x i32>
ret <2 x i32> %z
}
define <2 x i64> @fun5(<2 x i16> %val1) {
; CHECK-LABEL: fun5:
; CHECK: vuplhh %v0, %v24
; CHECK-NEXT: vuplhf %v24, %v0
; CHECK-NEXT: br %r14
%z = zext <2 x i16> %val1 to <2 x i64>
ret <2 x i64> %z
}
define <2 x i64> @fun6(<2 x i32> %val1) {
; CHECK-LABEL: fun6:
; CHECK: vuplhf %v24, %v24
; CHECK-NEXT: br %r14
%z = zext <2 x i32> %val1 to <2 x i64>
ret <2 x i64> %z
}
define <4 x i16> @fun7(<4 x i8> %val1) {
; CHECK-LABEL: fun7:
; CHECK: vuplhb %v24, %v24
; CHECK-NEXT: br %r14
%z = zext <4 x i8> %val1 to <4 x i16>
ret <4 x i16> %z
}
define <4 x i32> @fun8(<4 x i8> %val1) {
; CHECK-LABEL: fun8:
; CHECK: vuplhb %v0, %v24
; CHECK-NEXT: vuplhh %v24, %v0
; CHECK-NEXT: br %r14
%z = zext <4 x i8> %val1 to <4 x i32>
ret <4 x i32> %z
}
define <4 x i32> @fun9(<4 x i16> %val1) {
; CHECK-LABEL: fun9:
; CHECK: vuplhh %v24, %v24
; CHECK-NEXT: br %r14
%z = zext <4 x i16> %val1 to <4 x i32>
ret <4 x i32> %z
}
define <8 x i16> @fun10(<8 x i8> %val1) {
; CHECK-LABEL: fun10:
; CHECK: vuplhb %v24, %v24
; CHECK-NEXT: br %r14
%z = zext <8 x i8> %val1 to <8 x i16>
ret <8 x i16> %z
}