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[CodeGen][NFC] Regenerate load-combine test with update_llc_test.
To prepare for D27861.
This commit is contained in:
Clement Courbet
parent
97e9d6eacf
commit
e88e0737f1
@ -1,10 +1,12 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=arm64eb-unknown | FileCheck %s
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; i8* p; // p is 4 byte aligned
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; ((i32) p[0] << 24) | ((i32) p[1] << 16) | ((i32) p[2] << 8) | (i32) p[3]
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define i32 @load_i32_by_i8_big_endian(i32* %arg) {
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; CHECK-LABEL: load_i32_by_i8_big_endian:
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; CHECK: ldr w0, [x0]
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr w0, [x0]
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; CHECK-NEXT: ret
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%tmp = bitcast i32* %arg to i8*
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%tmp1 = load i8, i8* %tmp, align 4
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@ -31,7 +33,8 @@ define i32 @load_i32_by_i8_big_endian(i32* %arg) {
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; ((i32) (((i16) p[0] << 8) | (i16) p[1]) << 16) | (i32) (((i16) p[3] << 8) | (i16) p[4])
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define i32 @load_i32_by_i16_by_i8_big_endian(i32* %arg) {
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; CHECK-LABEL: load_i32_by_i16_by_i8_big_endian:
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; CHECK: ldr w0, [x0]
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr w0, [x0]
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; CHECK-NEXT: ret
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%tmp = bitcast i32* %arg to i8*
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%tmp1 = load i8, i8* %tmp, align 4
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@ -60,7 +63,8 @@ define i32 @load_i32_by_i16_by_i8_big_endian(i32* %arg) {
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; ((i32) p[0] << 16) | (i32) p[1]
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define i32 @load_i32_by_i16(i32* %arg) {
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; CHECK-LABEL: load_i32_by_i16:
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; CHECK: ldr w0, [x0]
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr w0, [x0]
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; CHECK-NEXT: ret
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%tmp = bitcast i32* %arg to i16*
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%tmp1 = load i16, i16* %tmp, align 4
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@ -78,7 +82,8 @@ define i32 @load_i32_by_i16(i32* %arg) {
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; (i32) (p_16[0] << 16) | ((i32) p[2] << 8) | (i32) p[3]
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define i32 @load_i32_by_i16_i8(i32* %arg) {
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; CHECK-LABEL: load_i32_by_i16_i8:
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; CHECK: ldr w0, [x0]
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr w0, [x0]
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; CHECK-NEXT: ret
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%tmp = bitcast i32* %arg to i16*
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%tmp1 = bitcast i32* %arg to i8*
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@ -101,7 +106,8 @@ define i32 @load_i32_by_i16_i8(i32* %arg) {
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; (i64) p[0] | ((i64) p[1] << 8) | ((i64) p[2] << 16) | ((i64) p[3] << 24) | ((i64) p[4] << 32) | ((i64) p[5] << 40) | ((i64) p[6] << 48) | ((i64) p[7] << 56)
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define i64 @load_i64_by_i8_bswap(i64* %arg) {
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; CHECK-LABEL: load_i64_by_i8_bswap:
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; CHECK: ldr x8, [x0]
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr x8, [x0]
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; CHECK-NEXT: rev x0, x8
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; CHECK-NEXT: ret
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%tmp = bitcast i64* %arg to i8*
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@ -149,7 +155,8 @@ define i64 @load_i64_by_i8_bswap(i64* %arg) {
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; ((i64) p[0] << 56) | ((i64) p[1] << 48) | ((i64) p[2] << 40) | ((i64) p[3] << 32) | ((i64) p[4] << 24) | ((i64) p[5] << 16) | ((i64) p[6] << 8) | (i64) p[7]
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define i64 @load_i64_by_i8(i64* %arg) {
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; CHECK-LABEL: load_i64_by_i8:
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; CHECK: ldr x0, [x0]
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr x0, [x0]
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; CHECK-NEXT: ret
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%tmp = bitcast i64* %arg to i8*
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%tmp1 = load i8, i8* %tmp, align 8
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@ -196,7 +203,8 @@ define i64 @load_i64_by_i8(i64* %arg) {
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; (i32) p[1] | ((i32) p[2] << 8) | ((i32) p[3] << 16) | ((i32) p[4] << 24)
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define i32 @load_i32_by_i8_nonzero_offset(i32* %arg) {
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; CHECK-LABEL: load_i32_by_i8_nonzero_offset:
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; CHECK: ldur w8, [x0, #1]
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldur w8, [x0, #1]
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; CHECK-NEXT: rev w0, w8
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; CHECK-NEXT: ret
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@ -226,7 +234,8 @@ define i32 @load_i32_by_i8_nonzero_offset(i32* %arg) {
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; (i32) p[-4] | ((i32) p[-3] << 8) | ((i32) p[-2] << 16) | ((i32) p[-1] << 24)
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define i32 @load_i32_by_i8_neg_offset(i32* %arg) {
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; CHECK-LABEL: load_i32_by_i8_neg_offset:
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; CHECK: ldur w8, [x0, #-4]
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldur w8, [x0, #-4]
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; CHECK-NEXT: rev w0, w8
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; CHECK-NEXT: ret
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@ -256,7 +265,8 @@ define i32 @load_i32_by_i8_neg_offset(i32* %arg) {
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; (i32) p[4] | ((i32) p[3] << 8) | ((i32) p[2] << 16) | ((i32) p[1] << 24)
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define i32 @load_i32_by_i8_nonzero_offset_bswap(i32* %arg) {
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; CHECK-LABEL: load_i32_by_i8_nonzero_offset_bswap:
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; CHECK: ldur w0, [x0, #1]
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldur w0, [x0, #1]
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; CHECK-NEXT: ret
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%tmp = bitcast i32* %arg to i8*
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@ -285,7 +295,8 @@ define i32 @load_i32_by_i8_nonzero_offset_bswap(i32* %arg) {
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; (i32) p[-1] | ((i32) p[-2] << 8) | ((i32) p[-3] << 16) | ((i32) p[-4] << 24)
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define i32 @load_i32_by_i8_neg_offset_bswap(i32* %arg) {
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; CHECK-LABEL: load_i32_by_i8_neg_offset_bswap:
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; CHECK: ldur w0, [x0, #-4]
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldur w0, [x0, #-4]
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; CHECK-NEXT: ret
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%tmp = bitcast i32* %arg to i8*
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@ -316,7 +327,8 @@ declare i16 @llvm.bswap.i16(i16)
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; (i32) bswap(p[0]) | (i32) bswap(p[1] << 16)
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define i32 @load_i32_by_bswap_i16(i32* %arg) {
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; CHECK-LABEL: load_i32_by_bswap_i16:
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; CHECK: ldr w8, [x0]
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr w8, [x0]
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; CHECK-NEXT: rev w0, w8
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; CHECK-NEXT: ret
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%tmp = bitcast i32* %arg to i16*
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@ -336,7 +348,8 @@ define i32 @load_i32_by_bswap_i16(i32* %arg) {
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; (i32) p[1] | (sext(p[0] << 16) to i32)
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define i32 @load_i32_by_sext_i16(i32* %arg) {
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; CHECK-LABEL: load_i32_by_sext_i16:
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; CHECK: ldr w0, [x0]
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr w0, [x0]
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; CHECK-NEXT: ret
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%tmp = bitcast i32* %arg to i16*
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%tmp1 = load i16, i16* %tmp, align 4
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@ -354,7 +367,8 @@ define i32 @load_i32_by_sext_i16(i32* %arg) {
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; (i32) p[i] | ((i32) p[i + 1] << 8) | ((i32) p[i + 2] << 16) | ((i32) p[i + 3] << 24)
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define i32 @load_i32_by_i8_base_offset_index(i8* %arg, i32 %i) {
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; CHECK-LABEL: load_i32_by_i8_base_offset_index:
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; CHECK: add x8, x0, w1, uxtw
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; CHECK: // %bb.0:
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; CHECK-NEXT: add x8, x0, w1, uxtw
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; CHECK-NEXT: ldr w8, [x8, #12]
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; CHECK-NEXT: rev w0, w8
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; CHECK-NEXT: ret
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@ -392,7 +406,8 @@ define i32 @load_i32_by_i8_base_offset_index(i8* %arg, i32 %i) {
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; (i32) p[i + 1] | ((i32) p[i + 2] << 8) | ((i32) p[i + 3] << 16) | ((i32) p[i + 4] << 24)
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define i32 @load_i32_by_i8_base_offset_index_2(i8* %arg, i32 %i) {
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; CHECK-LABEL: load_i32_by_i8_base_offset_index_2:
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; CHECK: add x8, x0, w1, uxtw
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; CHECK: // %bb.0:
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; CHECK-NEXT: add x8, x0, w1, uxtw
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; CHECK-NEXT: ldur w8, [x8, #13]
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; CHECK-NEXT: rev w0, w8
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; CHECK-NEXT: ret
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@ -429,7 +444,8 @@ define i32 @load_i32_by_i8_base_offset_index_2(i8* %arg, i32 %i) {
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; (i32) p[0] | ((i32) p[1] << 8)
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define i32 @zext_load_i32_by_i8(i32* %arg) {
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; CHECK-LABEL: zext_load_i32_by_i8:
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; CHECK: ldrb w8, [x0]
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldrb w8, [x0]
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; CHECK-NEXT: ldrb w9, [x0, #1]
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; CHECK-NEXT: bfi w8, w9, #8, #8
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; CHECK-NEXT: mov w0, w8
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@ -451,7 +467,8 @@ define i32 @zext_load_i32_by_i8(i32* %arg) {
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; ((i32) p[0] << 8) | ((i32) p[1] << 16)
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define i32 @zext_load_i32_by_i8_shl_8(i32* %arg) {
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; CHECK-LABEL: zext_load_i32_by_i8_shl_8:
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; CHECK: ldrb w8, [x0]
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldrb w8, [x0]
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; CHECK-NEXT: ldrb w9, [x0, #1]
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; CHECK-NEXT: lsl w0, w8, #8
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; CHECK-NEXT: bfi w0, w9, #16, #8
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@ -474,7 +491,8 @@ define i32 @zext_load_i32_by_i8_shl_8(i32* %arg) {
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; ((i32) p[0] << 16) | ((i32) p[1] << 24)
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define i32 @zext_load_i32_by_i8_shl_16(i32* %arg) {
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; CHECK-LABEL: zext_load_i32_by_i8_shl_16:
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; CHECK: ldrb w8, [x0]
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldrb w8, [x0]
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; CHECK-NEXT: ldrb w9, [x0, #1]
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; CHECK-NEXT: lsl w0, w8, #16
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; CHECK-NEXT: bfi w0, w9, #24, #8
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@ -496,7 +514,8 @@ define i32 @zext_load_i32_by_i8_shl_16(i32* %arg) {
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; (i32) p[1] | ((i32) p[0] << 8)
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define i32 @zext_load_i32_by_i8_bswap(i32* %arg) {
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; CHECK-LABEL: zext_load_i32_by_i8_bswap:
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; CHECK: ldrb w8, [x0, #1]
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldrb w8, [x0, #1]
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; CHECK-NEXT: ldrb w9, [x0]
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; CHECK-NEXT: bfi w8, w9, #8, #8
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; CHECK-NEXT: mov w0, w8
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@ -518,7 +537,8 @@ define i32 @zext_load_i32_by_i8_bswap(i32* %arg) {
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; ((i32) p[1] << 8) | ((i32) p[0] << 16)
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define i32 @zext_load_i32_by_i8_bswap_shl_8(i32* %arg) {
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; CHECK-LABEL: zext_load_i32_by_i8_bswap_shl_8:
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; CHECK: ldrb w8, [x0, #1]
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldrb w8, [x0, #1]
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; CHECK-NEXT: ldrb w9, [x0]
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; CHECK-NEXT: lsl w0, w8, #8
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; CHECK-NEXT: bfi w0, w9, #16, #8
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@ -541,7 +561,8 @@ define i32 @zext_load_i32_by_i8_bswap_shl_8(i32* %arg) {
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; ((i32) p[1] << 16) | ((i32) p[0] << 24)
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define i32 @zext_load_i32_by_i8_bswap_shl_16(i32* %arg) {
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; CHECK-LABEL: zext_load_i32_by_i8_bswap_shl_16:
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; CHECK: ldrb w8, [x0, #1]
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldrb w8, [x0, #1]
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; CHECK-NEXT: ldrb w9, [x0]
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; CHECK-NEXT: lsl w0, w8, #16
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; CHECK-NEXT: bfi w0, w9, #24, #8
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@ -568,7 +589,8 @@ define i32 @zext_load_i32_by_i8_bswap_shl_16(i32* %arg) {
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; because in the original DAG we don't have p[1] address available
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define i16 @load_i16_from_nonzero_offset(i8* %p) {
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; CHECK-LABEL: load_i16_from_nonzero_offset:
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; CHECK: ldrh w8, [x0]
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldrh w8, [x0]
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; CHECK-NEXT: ldrb w0, [x0, #2]
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; CHECK-NEXT: bfi w0, w8, #8, #24
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; CHECK-NEXT: ret
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@ -1,10 +1,12 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=arm64-unknown | FileCheck %s
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; i8* p; // p is 1 byte aligned
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; (i32) p[0] | ((i32) p[1] << 8) | ((i32) p[2] << 16) | ((i32) p[3] << 24)
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define i32 @load_i32_by_i8_unaligned(i32* %arg) {
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; CHECK-LABEL: load_i32_by_i8_unaligned:
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; CHECK: ldr w0, [x0]
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr w0, [x0]
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; CHECK-NEXT: ret
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%tmp = bitcast i32* %arg to i8*
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%tmp1 = getelementptr inbounds i8, i8* %tmp, i32 0
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@ -32,7 +34,8 @@ define i32 @load_i32_by_i8_unaligned(i32* %arg) {
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; (i32) p[0] | ((i32) p[1] << 8) | ((i32) p[2] << 16) | ((i32) p[3] << 24)
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define i32 @load_i32_by_i8_aligned(i32* %arg) {
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; CHECK-LABEL: load_i32_by_i8_aligned:
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; CHECK: ldr w0, [x0]
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr w0, [x0]
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; CHECK-NEXT: ret
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%tmp = bitcast i32* %arg to i8*
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%tmp1 = getelementptr inbounds i8, i8* %tmp, i32 0
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@ -60,7 +63,8 @@ define i32 @load_i32_by_i8_aligned(i32* %arg) {
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; ((i32) p[0] << 24) | ((i32) p[1] << 16) | ((i32) p[2] << 8) | (i32) p[3]
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define i32 @load_i32_by_i8_bswap(i32* %arg) {
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; CHECK-LABEL: load_i32_by_i8_bswap:
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; CHECK: ldr w8, [x0]
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr w8, [x0]
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; CHECK-NEXT: rev w0, w8
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; CHECK-NEXT: ret
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%tmp = bitcast i32* %arg to i8*
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@ -88,7 +92,8 @@ define i32 @load_i32_by_i8_bswap(i32* %arg) {
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; (i64) p[0] | ((i64) p[1] << 8) | ((i64) p[2] << 16) | ((i64) p[3] << 24) | ((i64) p[4] << 32) | ((i64) p[5] << 40) | ((i64) p[6] << 48) | ((i64) p[7] << 56)
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define i64 @load_i64_by_i8(i64* %arg) {
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; CHECK-LABEL: load_i64_by_i8:
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; CHECK: ldr x0, [x0]
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr x0, [x0]
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; CHECK-NEXT: ret
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%tmp = bitcast i64* %arg to i8*
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%tmp1 = load i8, i8* %tmp, align 8
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@ -135,7 +140,8 @@ define i64 @load_i64_by_i8(i64* %arg) {
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; ((i64) p[0] << 56) | ((i64) p[1] << 48) | ((i64) p[2] << 40) | ((i64) p[3] << 32) | ((i64) p[4] << 24) | ((i64) p[5] << 16) | ((i64) p[6] << 8) | (i64) p[7]
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define i64 @load_i64_by_i8_bswap(i64* %arg) {
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; CHECK-LABEL: load_i64_by_i8_bswap:
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; CHECK: ldr x8, [x0]
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr x8, [x0]
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; CHECK-NEXT: rev x0, x8
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; CHECK-NEXT: ret
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%tmp = bitcast i64* %arg to i8*
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@ -183,7 +189,8 @@ define i64 @load_i64_by_i8_bswap(i64* %arg) {
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; (i32) p[1] | ((i32) p[2] << 8) | ((i32) p[3] << 16) | ((i32) p[4] << 24)
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define i32 @load_i32_by_i8_nonzero_offset(i32* %arg) {
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; CHECK-LABEL: load_i32_by_i8_nonzero_offset:
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; CHECK: ldur w0, [x0, #1]
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldur w0, [x0, #1]
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; CHECK-NEXT: ret
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%tmp = bitcast i32* %arg to i8*
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@ -212,7 +219,8 @@ define i32 @load_i32_by_i8_nonzero_offset(i32* %arg) {
|
||||
; (i32) p[-4] | ((i32) p[-3] << 8) | ((i32) p[-2] << 16) | ((i32) p[-1] << 24)
|
||||
define i32 @load_i32_by_i8_neg_offset(i32* %arg) {
|
||||
; CHECK-LABEL: load_i32_by_i8_neg_offset:
|
||||
; CHECK: ldur w0, [x0, #-4]
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldur w0, [x0, #-4]
|
||||
; CHECK-NEXT: ret
|
||||
|
||||
%tmp = bitcast i32* %arg to i8*
|
||||
@ -241,7 +249,8 @@ define i32 @load_i32_by_i8_neg_offset(i32* %arg) {
|
||||
; (i32) p[4] | ((i32) p[3] << 8) | ((i32) p[2] << 16) | ((i32) p[1] << 24)
|
||||
define i32 @load_i32_by_i8_nonzero_offset_bswap(i32* %arg) {
|
||||
; CHECK-LABEL: load_i32_by_i8_nonzero_offset_bswap:
|
||||
; CHECK: ldur w8, [x0, #1]
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldur w8, [x0, #1]
|
||||
; CHECK-NEXT: rev w0, w8
|
||||
; CHECK-NEXT: ret
|
||||
|
||||
@ -271,7 +280,8 @@ define i32 @load_i32_by_i8_nonzero_offset_bswap(i32* %arg) {
|
||||
; (i32) p[-1] | ((i32) p[-2] << 8) | ((i32) p[-3] << 16) | ((i32) p[-4] << 24)
|
||||
define i32 @load_i32_by_i8_neg_offset_bswap(i32* %arg) {
|
||||
; CHECK-LABEL: load_i32_by_i8_neg_offset_bswap:
|
||||
; CHECK: ldur w8, [x0, #-4]
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldur w8, [x0, #-4]
|
||||
; CHECK-NEXT: rev w0, w8
|
||||
; CHECK-NEXT: ret
|
||||
|
||||
@ -303,7 +313,8 @@ declare i16 @llvm.bswap.i16(i16)
|
||||
; (i32) bswap(p[1]) | (i32) bswap(p[0] << 16)
|
||||
define i32 @load_i32_by_bswap_i16(i32* %arg) {
|
||||
; CHECK-LABEL: load_i32_by_bswap_i16:
|
||||
; CHECK: ldr w8, [x0]
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldr w8, [x0]
|
||||
; CHECK-NEXT: rev w0, w8
|
||||
; CHECK-NEXT: ret
|
||||
|
||||
@ -324,7 +335,8 @@ define i32 @load_i32_by_bswap_i16(i32* %arg) {
|
||||
; (i32) p[0] | (sext(p[1] << 16) to i32)
|
||||
define i32 @load_i32_by_sext_i16(i32* %arg) {
|
||||
; CHECK-LABEL: load_i32_by_sext_i16:
|
||||
; CHECK: ldr w0, [x0]
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldr w0, [x0]
|
||||
; CHECK-NEXT: ret
|
||||
%tmp = bitcast i32* %arg to i16*
|
||||
%tmp1 = load i16, i16* %tmp, align 4
|
||||
@ -342,7 +354,8 @@ define i32 @load_i32_by_sext_i16(i32* %arg) {
|
||||
; (i32) p[i] | ((i32) p[i + 1] << 8) | ((i32) p[i + 2] << 16) | ((i32) p[i + 3] << 24)
|
||||
define i32 @load_i32_by_i8_base_offset_index(i8* %arg, i32 %i) {
|
||||
; CHECK-LABEL: load_i32_by_i8_base_offset_index:
|
||||
; CHECK: add x8, x0, w1, uxtw
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: add x8, x0, w1, uxtw
|
||||
; CHECK-NEXT: ldr w0, [x8, #12]
|
||||
; CHECK-NEXT: ret
|
||||
%tmp = add nuw nsw i32 %i, 3
|
||||
@ -379,7 +392,8 @@ define i32 @load_i32_by_i8_base_offset_index(i8* %arg, i32 %i) {
|
||||
; (i32) p[i + 1] | ((i32) p[i + 2] << 8) | ((i32) p[i + 3] << 16) | ((i32) p[i + 4] << 24)
|
||||
define i32 @load_i32_by_i8_base_offset_index_2(i8* %arg, i32 %i) {
|
||||
; CHECK-LABEL: load_i32_by_i8_base_offset_index_2:
|
||||
; CHECK: add x8, x0, w1, uxtw
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: add x8, x0, w1, uxtw
|
||||
; CHECK-NEXT: ldur w0, [x8, #13]
|
||||
; CHECK-NEXT: ret
|
||||
%tmp = add nuw nsw i32 %i, 4
|
||||
@ -416,7 +430,8 @@ define i32 @load_i32_by_i8_base_offset_index_2(i8* %arg, i32 %i) {
|
||||
; (i32) p[0] | ((i32) p[1] << 8)
|
||||
define i32 @zext_load_i32_by_i8(i32* %arg) {
|
||||
; CHECK-LABEL: zext_load_i32_by_i8:
|
||||
; CHECK: ldrb w8, [x0]
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldrb w8, [x0]
|
||||
; CHECK-NEXT: ldrb w9, [x0, #1]
|
||||
; CHECK-NEXT: bfi w8, w9, #8, #8
|
||||
; CHECK-NEXT: mov w0, w8
|
||||
@ -438,7 +453,8 @@ define i32 @zext_load_i32_by_i8(i32* %arg) {
|
||||
; ((i32) p[0] << 8) | ((i32) p[1] << 16)
|
||||
define i32 @zext_load_i32_by_i8_shl_8(i32* %arg) {
|
||||
; CHECK-LABEL: zext_load_i32_by_i8_shl_8:
|
||||
; CHECK: ldrb w8, [x0]
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldrb w8, [x0]
|
||||
; CHECK-NEXT: ldrb w9, [x0, #1]
|
||||
; CHECK-NEXT: lsl w0, w8, #8
|
||||
; CHECK-NEXT: bfi w0, w9, #16, #8
|
||||
@ -461,7 +477,8 @@ define i32 @zext_load_i32_by_i8_shl_8(i32* %arg) {
|
||||
; ((i32) p[0] << 16) | ((i32) p[1] << 24)
|
||||
define i32 @zext_load_i32_by_i8_shl_16(i32* %arg) {
|
||||
; CHECK-LABEL: zext_load_i32_by_i8_shl_16:
|
||||
; CHECK: ldrb w8, [x0]
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldrb w8, [x0]
|
||||
; CHECK-NEXT: ldrb w9, [x0, #1]
|
||||
; CHECK-NEXT: lsl w0, w8, #16
|
||||
; CHECK-NEXT: bfi w0, w9, #24, #8
|
||||
@ -483,7 +500,8 @@ define i32 @zext_load_i32_by_i8_shl_16(i32* %arg) {
|
||||
; (i32) p[1] | ((i32) p[0] << 8)
|
||||
define i32 @zext_load_i32_by_i8_bswap(i32* %arg) {
|
||||
; CHECK-LABEL: zext_load_i32_by_i8_bswap:
|
||||
; CHECK: ldrb w8, [x0, #1]
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldrb w8, [x0, #1]
|
||||
; CHECK-NEXT: ldrb w9, [x0]
|
||||
; CHECK-NEXT: bfi w8, w9, #8, #8
|
||||
; CHECK-NEXT: mov w0, w8
|
||||
@ -505,7 +523,8 @@ define i32 @zext_load_i32_by_i8_bswap(i32* %arg) {
|
||||
; ((i32) p[1] << 8) | ((i32) p[0] << 16)
|
||||
define i32 @zext_load_i32_by_i8_bswap_shl_8(i32* %arg) {
|
||||
; CHECK-LABEL: zext_load_i32_by_i8_bswap_shl_8:
|
||||
; CHECK: ldrb w8, [x0, #1]
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldrb w8, [x0, #1]
|
||||
; CHECK-NEXT: ldrb w9, [x0]
|
||||
; CHECK-NEXT: lsl w0, w8, #8
|
||||
; CHECK-NEXT: bfi w0, w9, #16, #8
|
||||
@ -528,7 +547,8 @@ define i32 @zext_load_i32_by_i8_bswap_shl_8(i32* %arg) {
|
||||
; ((i32) p[1] << 16) | ((i32) p[0] << 24)
|
||||
define i32 @zext_load_i32_by_i8_bswap_shl_16(i32* %arg) {
|
||||
; CHECK-LABEL: zext_load_i32_by_i8_bswap_shl_16:
|
||||
; CHECK: ldrb w8, [x0, #1]
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldrb w8, [x0, #1]
|
||||
; CHECK-NEXT: ldrb w9, [x0]
|
||||
; CHECK-NEXT: lsl w0, w8, #16
|
||||
; CHECK-NEXT: bfi w0, w9, #24, #8
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc < %s -mtriple=armeb-unknown | FileCheck %s
|
||||
; RUN: llc < %s -mtriple=armv6eb-unknown | FileCheck %s --check-prefix=CHECK-ARMv6
|
||||
|
||||
@ -5,12 +6,15 @@
|
||||
; ((i32) p[0] << 24) | ((i32) p[1] << 16) | ((i32) p[2] << 8) | (i32) p[3]
|
||||
define i32 @load_i32_by_i8_big_endian(i32* %arg) {
|
||||
; CHECK-LABEL: load_i32_by_i8_big_endian:
|
||||
; CHECK: ldr r0, [r0]
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: ldr r0, [r0]
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
|
||||
;
|
||||
; CHECK-ARMv6-LABEL: load_i32_by_i8_big_endian:
|
||||
; CHECK-ARMv6: ldr r0, [r0]
|
||||
; CHECK-ARMv6: @ %bb.0:
|
||||
; CHECK-ARMv6-NEXT: ldr r0, [r0]
|
||||
; CHECK-ARMv6-NEXT: bx lr
|
||||
|
||||
%tmp = bitcast i32* %arg to i8*
|
||||
%tmp1 = load i8, i8* %tmp, align 4
|
||||
%tmp2 = zext i8 %tmp1 to i32
|
||||
@ -37,18 +41,23 @@ define i32 @load_i32_by_i8_big_endian(i32* %arg) {
|
||||
define i32 @load_i32_by_i8_bswap(i32* %arg) {
|
||||
; BSWAP is not supported by 32 bit target
|
||||
; CHECK-LABEL: load_i32_by_i8_bswap:
|
||||
; CHECK: ldr r0, [r0]
|
||||
; CHECK: and
|
||||
; CHECK-NEXT: and
|
||||
; CHECK-NEXT: orr
|
||||
; CHECK-NEXT: orr
|
||||
; CHECK-NEXT: orr
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: ldr r0, [r0]
|
||||
; CHECK-NEXT: mov r1, #65280
|
||||
; CHECK-NEXT: mov r2, #16711680
|
||||
; CHECK-NEXT: and r1, r1, r0, lsr #8
|
||||
; CHECK-NEXT: and r2, r2, r0, lsl #8
|
||||
; CHECK-NEXT: orr r1, r1, r0, lsr #24
|
||||
; CHECK-NEXT: orr r0, r2, r0, lsl #24
|
||||
; CHECK-NEXT: orr r0, r0, r1
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
|
||||
;
|
||||
; CHECK-ARMv6-LABEL: load_i32_by_i8_bswap:
|
||||
; CHECK-ARMv6: ldr r0, [r0]
|
||||
; CHECK-ARMv6: @ %bb.0:
|
||||
; CHECK-ARMv6-NEXT: ldr r0, [r0]
|
||||
; CHECK-ARMv6-NEXT: rev r0, r0
|
||||
; CHECK-ARMv6-NEXT: bx lr
|
||||
|
||||
%tmp = bitcast i32* %arg to i8*
|
||||
%tmp1 = getelementptr inbounds i8, i8* %tmp, i32 0
|
||||
%tmp2 = load i8, i8* %tmp1, align 4
|
||||
@ -75,12 +84,15 @@ define i32 @load_i32_by_i8_bswap(i32* %arg) {
|
||||
; ((i32) (((i16) p[0] << 8) | (i16) p[1]) << 16) | (i32) (((i16) p[3] << 8) | (i16) p[4])
|
||||
define i32 @load_i32_by_i16_by_i8_big_endian(i32* %arg) {
|
||||
; CHECK-LABEL: load_i32_by_i16_by_i8_big_endian:
|
||||
; CHECK: ldr r0, [r0]
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: ldr r0, [r0]
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
|
||||
;
|
||||
; CHECK-ARMv6-LABEL: load_i32_by_i16_by_i8_big_endian:
|
||||
; CHECK-ARMv6: ldr r0, [r0]
|
||||
; CHECK-ARMv6: @ %bb.0:
|
||||
; CHECK-ARMv6-NEXT: ldr r0, [r0]
|
||||
; CHECK-ARMv6-NEXT: bx lr
|
||||
|
||||
%tmp = bitcast i32* %arg to i8*
|
||||
%tmp1 = load i8, i8* %tmp, align 4
|
||||
%tmp2 = zext i8 %tmp1 to i16
|
||||
@ -108,12 +120,15 @@ define i32 @load_i32_by_i16_by_i8_big_endian(i32* %arg) {
|
||||
; ((i32) p[0] << 16) | (i32) p[1]
|
||||
define i32 @load_i32_by_i16(i32* %arg) {
|
||||
; CHECK-LABEL: load_i32_by_i16:
|
||||
; CHECK: ldr r0, [r0]
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: ldr r0, [r0]
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
|
||||
;
|
||||
; CHECK-ARMv6-LABEL: load_i32_by_i16:
|
||||
; CHECK-ARMv6: ldr r0, [r0]
|
||||
; CHECK-ARMv6: @ %bb.0:
|
||||
; CHECK-ARMv6-NEXT: ldr r0, [r0]
|
||||
; CHECK-ARMv6-NEXT: bx lr
|
||||
|
||||
%tmp = bitcast i32* %arg to i16*
|
||||
%tmp1 = load i16, i16* %tmp, align 4
|
||||
%tmp2 = zext i16 %tmp1 to i32
|
||||
@ -130,12 +145,15 @@ define i32 @load_i32_by_i16(i32* %arg) {
|
||||
; (i32) (p_16[0] << 16) | ((i32) p[2] << 8) | (i32) p[3]
|
||||
define i32 @load_i32_by_i16_i8(i32* %arg) {
|
||||
; CHECK-LABEL: load_i32_by_i16_i8:
|
||||
; CHECK: ldr r0, [r0]
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: ldr r0, [r0]
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
|
||||
;
|
||||
; CHECK-ARMv6-LABEL: load_i32_by_i16_i8:
|
||||
; CHECK-ARMv6: ldr r0, [r0]
|
||||
; CHECK-ARMv6: @ %bb.0:
|
||||
; CHECK-ARMv6-NEXT: ldr r0, [r0]
|
||||
; CHECK-ARMv6-NEXT: bx lr
|
||||
|
||||
%tmp = bitcast i32* %arg to i16*
|
||||
%tmp1 = bitcast i32* %arg to i8*
|
||||
%tmp2 = load i16, i16* %tmp, align 4
|
||||
@ -157,25 +175,32 @@ define i32 @load_i32_by_i16_i8(i32* %arg) {
|
||||
; (i64) p[0] | ((i64) p[1] << 8) | ((i64) p[2] << 16) | ((i64) p[3] << 24) | ((i64) p[4] << 32) | ((i64) p[5] << 40) | ((i64) p[6] << 48) | ((i64) p[7] << 56)
|
||||
define i64 @load_i64_by_i8_bswap(i64* %arg) {
|
||||
; CHECK-LABEL: load_i64_by_i8_bswap:
|
||||
; CHECK: ldr{{.*}}r0
|
||||
; CHECK: ldr{{.*}}r0
|
||||
; CHECK: and
|
||||
; CHECK-NEXT: and
|
||||
; CHECK-NEXT: orr
|
||||
; CHECK-NEXT: orr
|
||||
; CHECK-NEXT: and
|
||||
; CHECK-NEXT: orr
|
||||
; CHECK-NEXT: and
|
||||
; CHECK-NEXT: orr
|
||||
; CHECK-NEXT: orr
|
||||
; CHECK-NEXT: orr
|
||||
; CHECK: mov pc, lr
|
||||
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: push {r11, lr}
|
||||
; CHECK-NEXT: ldr r1, [r0]
|
||||
; CHECK-NEXT: mov r12, #65280
|
||||
; CHECK-NEXT: ldr r0, [r0, #4]
|
||||
; CHECK-NEXT: mov lr, #16711680
|
||||
; CHECK-NEXT: and r3, r12, r0, lsr #8
|
||||
; CHECK-NEXT: and r2, lr, r0, lsl #8
|
||||
; CHECK-NEXT: orr r3, r3, r0, lsr #24
|
||||
; CHECK-NEXT: orr r0, r2, r0, lsl #24
|
||||
; CHECK-NEXT: and r2, r12, r1, lsr #8
|
||||
; CHECK-NEXT: orr r0, r0, r3
|
||||
; CHECK-NEXT: and r3, lr, r1, lsl #8
|
||||
; CHECK-NEXT: orr r2, r2, r1, lsr #24
|
||||
; CHECK-NEXT: orr r1, r3, r1, lsl #24
|
||||
; CHECK-NEXT: orr r1, r1, r2
|
||||
; CHECK-NEXT: pop {r11, lr}
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
;
|
||||
; CHECK-ARMv6-LABEL: load_i64_by_i8_bswap:
|
||||
; CHECK-ARMv6: ldrd r2, r3, [r0]
|
||||
; CHECK-ARMv6: rev r0, r3
|
||||
; CHECK-ARMv6: rev r1, r2
|
||||
; CHECK-ARMv6: bx lr
|
||||
; CHECK-ARMv6: @ %bb.0:
|
||||
; CHECK-ARMv6-NEXT: ldrd r2, r3, [r0]
|
||||
; CHECK-ARMv6-NEXT: rev r0, r3
|
||||
; CHECK-ARMv6-NEXT: rev r1, r2
|
||||
; CHECK-ARMv6-NEXT: bx lr
|
||||
|
||||
%tmp = bitcast i64* %arg to i8*
|
||||
%tmp1 = load i8, i8* %tmp, align 8
|
||||
%tmp2 = zext i8 %tmp1 to i64
|
||||
@ -221,14 +246,17 @@ define i64 @load_i64_by_i8_bswap(i64* %arg) {
|
||||
; ((i64) p[0] << 56) | ((i64) p[1] << 48) | ((i64) p[2] << 40) | ((i64) p[3] << 32) | ((i64) p[4] << 24) | ((i64) p[5] << 16) | ((i64) p[6] << 8) | (i64) p[7]
|
||||
define i64 @load_i64_by_i8(i64* %arg) {
|
||||
; CHECK-LABEL: load_i64_by_i8:
|
||||
; CHECK: ldr r2, [r0]
|
||||
; CHECK: ldr r1, [r0, #4]
|
||||
; CHECK: mov r0, r2
|
||||
; CHECK: mov pc, lr
|
||||
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: ldr r2, [r0]
|
||||
; CHECK-NEXT: ldr r1, [r0, #4]
|
||||
; CHECK-NEXT: mov r0, r2
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
;
|
||||
; CHECK-ARMv6-LABEL: load_i64_by_i8:
|
||||
; CHECK-ARMv6: ldrd r0, r1, [r0]
|
||||
; CHECK-ARMv6: bx lr
|
||||
; CHECK-ARMv6: @ %bb.0:
|
||||
; CHECK-ARMv6-NEXT: ldrd r0, r1, [r0]
|
||||
; CHECK-ARMv6-NEXT: bx lr
|
||||
|
||||
%tmp = bitcast i64* %arg to i8*
|
||||
%tmp1 = load i8, i8* %tmp, align 8
|
||||
%tmp2 = zext i8 %tmp1 to i64
|
||||
@ -274,7 +302,8 @@ define i64 @load_i64_by_i8(i64* %arg) {
|
||||
; (i32) p[1] | ((i32) p[2] << 8) | ((i32) p[3] << 16) | ((i32) p[4] << 24)
|
||||
define i32 @load_i32_by_i8_nonzero_offset(i32* %arg) {
|
||||
; CHECK-LABEL: load_i32_by_i8_nonzero_offset:
|
||||
; CHECK: ldr r0, [r0, #1]
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: ldr r0, [r0, #1]
|
||||
; CHECK-NEXT: mov r1, #65280
|
||||
; CHECK-NEXT: mov r2, #16711680
|
||||
; CHECK-NEXT: and r1, r1, r0, lsr #8
|
||||
@ -283,12 +312,14 @@ define i32 @load_i32_by_i8_nonzero_offset(i32* %arg) {
|
||||
; CHECK-NEXT: orr r0, r2, r0, lsl #24
|
||||
; CHECK-NEXT: orr r0, r0, r1
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
|
||||
;
|
||||
; CHECK-ARMv6-LABEL: load_i32_by_i8_nonzero_offset:
|
||||
; CHECK-ARMv6: ldr r0, [r0, #1]
|
||||
; CHECK-ARMv6: @ %bb.0:
|
||||
; CHECK-ARMv6-NEXT: ldr r0, [r0, #1]
|
||||
; CHECK-ARMv6-NEXT: rev r0, r0
|
||||
; CHECK-ARMv6-NEXT: bx lr
|
||||
|
||||
|
||||
%tmp = bitcast i32* %arg to i8*
|
||||
%tmp1 = getelementptr inbounds i8, i8* %tmp, i32 1
|
||||
%tmp2 = load i8, i8* %tmp1, align 4
|
||||
@ -315,7 +346,8 @@ define i32 @load_i32_by_i8_nonzero_offset(i32* %arg) {
|
||||
; (i32) p[-4] | ((i32) p[-3] << 8) | ((i32) p[-2] << 16) | ((i32) p[-1] << 24)
|
||||
define i32 @load_i32_by_i8_neg_offset(i32* %arg) {
|
||||
; CHECK-LABEL: load_i32_by_i8_neg_offset:
|
||||
; CHECK: ldr r0, [r0, #-4]
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: ldr r0, [r0, #-4]
|
||||
; CHECK-NEXT: mov r1, #65280
|
||||
; CHECK-NEXT: mov r2, #16711680
|
||||
; CHECK-NEXT: and r1, r1, r0, lsr #8
|
||||
@ -324,12 +356,14 @@ define i32 @load_i32_by_i8_neg_offset(i32* %arg) {
|
||||
; CHECK-NEXT: orr r0, r2, r0, lsl #24
|
||||
; CHECK-NEXT: orr r0, r0, r1
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
|
||||
;
|
||||
; CHECK-ARMv6-LABEL: load_i32_by_i8_neg_offset:
|
||||
; CHECK-ARMv6: ldr r0, [r0, #-4]
|
||||
; CHECK-ARMv6: @ %bb.0:
|
||||
; CHECK-ARMv6-NEXT: ldr r0, [r0, #-4]
|
||||
; CHECK-ARMv6-NEXT: rev r0, r0
|
||||
; CHECK-ARMv6-NEXT: bx lr
|
||||
|
||||
|
||||
%tmp = bitcast i32* %arg to i8*
|
||||
%tmp1 = getelementptr inbounds i8, i8* %tmp, i32 -4
|
||||
%tmp2 = load i8, i8* %tmp1, align 4
|
||||
@ -356,13 +390,16 @@ define i32 @load_i32_by_i8_neg_offset(i32* %arg) {
|
||||
; (i32) p[4] | ((i32) p[3] << 8) | ((i32) p[2] << 16) | ((i32) p[1] << 24)
|
||||
define i32 @load_i32_by_i8_nonzero_offset_bswap(i32* %arg) {
|
||||
; CHECK-LABEL: load_i32_by_i8_nonzero_offset_bswap:
|
||||
; CHECK: ldr r0, [r0, #1]
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: ldr r0, [r0, #1]
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
|
||||
;
|
||||
; CHECK-ARMv6-LABEL: load_i32_by_i8_nonzero_offset_bswap:
|
||||
; CHECK-ARMv6: ldr r0, [r0, #1]
|
||||
; CHECK-ARMv6: @ %bb.0:
|
||||
; CHECK-ARMv6-NEXT: ldr r0, [r0, #1]
|
||||
; CHECK-ARMv6-NEXT: bx lr
|
||||
|
||||
|
||||
%tmp = bitcast i32* %arg to i8*
|
||||
%tmp1 = getelementptr inbounds i8, i8* %tmp, i32 4
|
||||
%tmp2 = load i8, i8* %tmp1, align 1
|
||||
@ -389,13 +426,16 @@ define i32 @load_i32_by_i8_nonzero_offset_bswap(i32* %arg) {
|
||||
; (i32) p[-1] | ((i32) p[-2] << 8) | ((i32) p[-3] << 16) | ((i32) p[-4] << 24)
|
||||
define i32 @load_i32_by_i8_neg_offset_bswap(i32* %arg) {
|
||||
; CHECK-LABEL: load_i32_by_i8_neg_offset_bswap:
|
||||
; CHECK: ldr r0, [r0, #-4]
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: ldr r0, [r0, #-4]
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
|
||||
;
|
||||
; CHECK-ARMv6-LABEL: load_i32_by_i8_neg_offset_bswap:
|
||||
; CHECK-ARMv6: ldr r0, [r0, #-4]
|
||||
; CHECK-ARMv6: @ %bb.0:
|
||||
; CHECK-ARMv6-NEXT: ldr r0, [r0, #-4]
|
||||
; CHECK-ARMv6-NEXT: bx lr
|
||||
|
||||
|
||||
%tmp = bitcast i32* %arg to i8*
|
||||
%tmp1 = getelementptr inbounds i8, i8* %tmp, i32 -1
|
||||
%tmp2 = load i8, i8* %tmp1, align 1
|
||||
@ -424,7 +464,8 @@ declare i16 @llvm.bswap.i16(i16)
|
||||
; (i32) bswap(p[0]) | (i32) bswap(p[1] << 16)
|
||||
define i32 @load_i32_by_bswap_i16(i32* %arg) {
|
||||
; CHECK-LABEL: load_i32_by_bswap_i16:
|
||||
; CHECK: ldr r0, [r0]
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: ldr r0, [r0]
|
||||
; CHECK-NEXT: mov r1, #65280
|
||||
; CHECK-NEXT: mov r2, #16711680
|
||||
; CHECK-NEXT: and r1, r1, r0, lsr #8
|
||||
@ -433,12 +474,14 @@ define i32 @load_i32_by_bswap_i16(i32* %arg) {
|
||||
; CHECK-NEXT: orr r0, r2, r0, lsl #24
|
||||
; CHECK-NEXT: orr r0, r0, r1
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
|
||||
;
|
||||
; CHECK-ARMv6-LABEL: load_i32_by_bswap_i16:
|
||||
; CHECK-ARMv6: ldr r0, [r0]
|
||||
; CHECK-ARMv6: @ %bb.0:
|
||||
; CHECK-ARMv6-NEXT: ldr r0, [r0]
|
||||
; CHECK-ARMv6-NEXT: rev r0, r0
|
||||
; CHECK-ARMv6-NEXT: bx lr
|
||||
|
||||
|
||||
%tmp = bitcast i32* %arg to i16*
|
||||
%tmp1 = load i16, i16* %tmp, align 4
|
||||
%tmp11 = call i16 @llvm.bswap.i16(i16 %tmp1)
|
||||
@ -456,11 +499,13 @@ define i32 @load_i32_by_bswap_i16(i32* %arg) {
|
||||
; (i32) p[1] | (sext(p[0] << 16) to i32)
|
||||
define i32 @load_i32_by_sext_i16(i32* %arg) {
|
||||
; CHECK-LABEL: load_i32_by_sext_i16:
|
||||
; CHECK: ldr r0, [r0]
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: ldr r0, [r0]
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
;
|
||||
; CHECK-ARMv6-LABEL: load_i32_by_sext_i16:
|
||||
; CHECK-ARMv6: ldr r0, [r0]
|
||||
; CHECK-ARMv6: @ %bb.0:
|
||||
; CHECK-ARMv6-NEXT: ldr r0, [r0]
|
||||
; CHECK-ARMv6-NEXT: bx lr
|
||||
%tmp = bitcast i32* %arg to i16*
|
||||
%tmp1 = load i16, i16* %tmp, align 4
|
||||
@ -478,7 +523,8 @@ define i32 @load_i32_by_sext_i16(i32* %arg) {
|
||||
; (i32) p[i] | ((i32) p[i + 1] << 8) | ((i32) p[i + 2] << 16) | ((i32) p[i + 3] << 24)
|
||||
define i32 @load_i32_by_i8_base_offset_index(i8* %arg, i32 %i) {
|
||||
; CHECK-LABEL: load_i32_by_i8_base_offset_index:
|
||||
; CHECK: add r0, r0, r1
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: add r0, r0, r1
|
||||
; CHECK-NEXT: mov r1, #65280
|
||||
; CHECK-NEXT: mov r2, #16711680
|
||||
; CHECK-NEXT: ldr r0, [r0, #12]
|
||||
@ -490,7 +536,8 @@ define i32 @load_i32_by_i8_base_offset_index(i8* %arg, i32 %i) {
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
;
|
||||
; CHECK-ARMv6-LABEL: load_i32_by_i8_base_offset_index:
|
||||
; CHECK-ARMv6: add r0, r0, r1
|
||||
; CHECK-ARMv6: @ %bb.0:
|
||||
; CHECK-ARMv6-NEXT: add r0, r0, r1
|
||||
; CHECK-ARMv6-NEXT: ldr r0, [r0, #12]
|
||||
; CHECK-ARMv6-NEXT: rev r0, r0
|
||||
; CHECK-ARMv6-NEXT: bx lr
|
||||
@ -528,7 +575,8 @@ define i32 @load_i32_by_i8_base_offset_index(i8* %arg, i32 %i) {
|
||||
; (i32) p[i + 1] | ((i32) p[i + 2] << 8) | ((i32) p[i + 3] << 16) | ((i32) p[i + 4] << 24)
|
||||
define i32 @load_i32_by_i8_base_offset_index_2(i8* %arg, i32 %i) {
|
||||
; CHECK-LABEL: load_i32_by_i8_base_offset_index_2:
|
||||
; CHECK: add r0, r1, r0
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: add r0, r1, r0
|
||||
; CHECK-NEXT: mov r1, #65280
|
||||
; CHECK-NEXT: mov r2, #16711680
|
||||
; CHECK-NEXT: ldr r0, [r0, #13]
|
||||
@ -540,7 +588,8 @@ define i32 @load_i32_by_i8_base_offset_index_2(i8* %arg, i32 %i) {
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
;
|
||||
; CHECK-ARMv6-LABEL: load_i32_by_i8_base_offset_index_2:
|
||||
; CHECK-ARMv6: add r0, r1, r0
|
||||
; CHECK-ARMv6: @ %bb.0:
|
||||
; CHECK-ARMv6-NEXT: add r0, r1, r0
|
||||
; CHECK-ARMv6-NEXT: ldr r0, [r0, #13]
|
||||
; CHECK-ARMv6-NEXT: rev r0, r0
|
||||
; CHECK-ARMv6-NEXT: bx lr
|
||||
@ -579,13 +628,15 @@ define i32 @load_i32_by_i8_base_offset_index_2(i8* %arg, i32 %i) {
|
||||
; (i32) p[0] | ((i32) p[1] << 8)
|
||||
define i32 @zext_load_i32_by_i8(i32* %arg) {
|
||||
; CHECK-LABEL: zext_load_i32_by_i8:
|
||||
; CHECK: ldrb r1, [r0]
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: ldrb r1, [r0]
|
||||
; CHECK-NEXT: ldrb r0, [r0, #1]
|
||||
; CHECK-NEXT: orr r0, r1, r0, lsl #8
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
;
|
||||
; CHECK-ARMv6-LABEL: zext_load_i32_by_i8:
|
||||
; CHECK-ARMv6: ldrb r1, [r0]
|
||||
; CHECK-ARMv6: @ %bb.0:
|
||||
; CHECK-ARMv6-NEXT: ldrb r1, [r0]
|
||||
; CHECK-ARMv6-NEXT: ldrb r0, [r0, #1]
|
||||
; CHECK-ARMv6-NEXT: orr r0, r1, r0, lsl #8
|
||||
; CHECK-ARMv6-NEXT: bx lr
|
||||
@ -606,14 +657,16 @@ define i32 @zext_load_i32_by_i8(i32* %arg) {
|
||||
; ((i32) p[0] << 8) | ((i32) p[1] << 16)
|
||||
define i32 @zext_load_i32_by_i8_shl_8(i32* %arg) {
|
||||
; CHECK-LABEL: zext_load_i32_by_i8_shl_8:
|
||||
; CHECK: ldrb r1, [r0]
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: ldrb r1, [r0]
|
||||
; CHECK-NEXT: ldrb r0, [r0, #1]
|
||||
; CHECK-NEXT: lsl r0, r0, #16
|
||||
; CHECK-NEXT: orr r0, r0, r1, lsl #8
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
;
|
||||
; CHECK-ARMv6-LABEL: zext_load_i32_by_i8_shl_8:
|
||||
; CHECK-ARMv6: ldrb r1, [r0]
|
||||
; CHECK-ARMv6: @ %bb.0:
|
||||
; CHECK-ARMv6-NEXT: ldrb r1, [r0]
|
||||
; CHECK-ARMv6-NEXT: ldrb r0, [r0, #1]
|
||||
; CHECK-ARMv6-NEXT: lsl r0, r0, #16
|
||||
; CHECK-ARMv6-NEXT: orr r0, r0, r1, lsl #8
|
||||
@ -636,14 +689,16 @@ define i32 @zext_load_i32_by_i8_shl_8(i32* %arg) {
|
||||
; ((i32) p[0] << 16) | ((i32) p[1] << 24)
|
||||
define i32 @zext_load_i32_by_i8_shl_16(i32* %arg) {
|
||||
; CHECK-LABEL: zext_load_i32_by_i8_shl_16:
|
||||
; CHECK: ldrb r1, [r0]
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: ldrb r1, [r0]
|
||||
; CHECK-NEXT: ldrb r0, [r0, #1]
|
||||
; CHECK-NEXT: lsl r0, r0, #24
|
||||
; CHECK-NEXT: orr r0, r0, r1, lsl #16
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
;
|
||||
; CHECK-ARMv6-LABEL: zext_load_i32_by_i8_shl_16:
|
||||
; CHECK-ARMv6: ldrb r1, [r0]
|
||||
; CHECK-ARMv6: @ %bb.0:
|
||||
; CHECK-ARMv6-NEXT: ldrb r1, [r0]
|
||||
; CHECK-ARMv6-NEXT: ldrb r0, [r0, #1]
|
||||
; CHECK-ARMv6-NEXT: lsl r0, r0, #24
|
||||
; CHECK-ARMv6-NEXT: orr r0, r0, r1, lsl #16
|
||||
@ -666,13 +721,15 @@ define i32 @zext_load_i32_by_i8_shl_16(i32* %arg) {
|
||||
; (i32) p[1] | ((i32) p[0] << 8)
|
||||
define i32 @zext_load_i32_by_i8_bswap(i32* %arg) {
|
||||
; CHECK-LABEL: zext_load_i32_by_i8_bswap:
|
||||
; CHECK: ldrb r1, [r0]
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: ldrb r1, [r0]
|
||||
; CHECK-NEXT: ldrb r0, [r0, #1]
|
||||
; CHECK-NEXT: orr r0, r0, r1, lsl #8
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
;
|
||||
; CHECK-ARMv6-LABEL: zext_load_i32_by_i8_bswap:
|
||||
; CHECK-ARMv6: ldrb r1, [r0]
|
||||
; CHECK-ARMv6: @ %bb.0:
|
||||
; CHECK-ARMv6-NEXT: ldrb r1, [r0]
|
||||
; CHECK-ARMv6-NEXT: ldrb r0, [r0, #1]
|
||||
; CHECK-ARMv6-NEXT: orr r0, r0, r1, lsl #8
|
||||
; CHECK-ARMv6-NEXT: bx lr
|
||||
@ -693,14 +750,16 @@ define i32 @zext_load_i32_by_i8_bswap(i32* %arg) {
|
||||
; ((i32) p[1] << 8) | ((i32) p[0] << 16)
|
||||
define i32 @zext_load_i32_by_i8_bswap_shl_8(i32* %arg) {
|
||||
; CHECK-LABEL: zext_load_i32_by_i8_bswap_shl_8:
|
||||
; CHECK: ldrb r1, [r0]
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: ldrb r1, [r0]
|
||||
; CHECK-NEXT: ldrb r0, [r0, #1]
|
||||
; CHECK-NEXT: lsl r1, r1, #16
|
||||
; CHECK-NEXT: orr r0, r1, r0, lsl #8
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
;
|
||||
; CHECK-ARMv6-LABEL: zext_load_i32_by_i8_bswap_shl_8:
|
||||
; CHECK-ARMv6: ldrb r1, [r0]
|
||||
; CHECK-ARMv6: @ %bb.0:
|
||||
; CHECK-ARMv6-NEXT: ldrb r1, [r0]
|
||||
; CHECK-ARMv6-NEXT: ldrb r0, [r0, #1]
|
||||
; CHECK-ARMv6-NEXT: lsl r1, r1, #16
|
||||
; CHECK-ARMv6-NEXT: orr r0, r1, r0, lsl #8
|
||||
@ -723,14 +782,16 @@ define i32 @zext_load_i32_by_i8_bswap_shl_8(i32* %arg) {
|
||||
; ((i32) p[1] << 16) | ((i32) p[0] << 24)
|
||||
define i32 @zext_load_i32_by_i8_bswap_shl_16(i32* %arg) {
|
||||
; CHECK-LABEL: zext_load_i32_by_i8_bswap_shl_16:
|
||||
; CHECK: ldrb r1, [r0]
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: ldrb r1, [r0]
|
||||
; CHECK-NEXT: ldrb r0, [r0, #1]
|
||||
; CHECK-NEXT: lsl r1, r1, #24
|
||||
; CHECK-NEXT: orr r0, r1, r0, lsl #16
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
;
|
||||
; CHECK-ARMv6-LABEL: zext_load_i32_by_i8_bswap_shl_16:
|
||||
; CHECK-ARMv6: ldrb r1, [r0]
|
||||
; CHECK-ARMv6: @ %bb.0:
|
||||
; CHECK-ARMv6-NEXT: ldrb r1, [r0]
|
||||
; CHECK-ARMv6-NEXT: ldrb r0, [r0, #1]
|
||||
; CHECK-ARMv6-NEXT: lsl r1, r1, #24
|
||||
; CHECK-ARMv6-NEXT: orr r0, r1, r0, lsl #16
|
||||
@ -757,13 +818,15 @@ define i32 @zext_load_i32_by_i8_bswap_shl_16(i32* %arg) {
|
||||
; because in the original DAG we don't have p[1] address available
|
||||
define i16 @load_i16_from_nonzero_offset(i8* %p) {
|
||||
; CHECK-LABEL: load_i16_from_nonzero_offset:
|
||||
; CHECK: ldrh r1, [r0]
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: ldrh r1, [r0]
|
||||
; CHECK-NEXT: ldrb r0, [r0, #2]
|
||||
; CHECK-NEXT: orr r0, r0, r1, lsl #8
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
;
|
||||
; CHECK-ARMv6-LABEL: load_i16_from_nonzero_offset:
|
||||
; CHECK-ARMv6: ldrh r1, [r0]
|
||||
; CHECK-ARMv6: @ %bb.0:
|
||||
; CHECK-ARMv6-NEXT: ldrh r1, [r0]
|
||||
; CHECK-ARMv6-NEXT: ldrb r0, [r0, #2]
|
||||
; CHECK-ARMv6-NEXT: orr r0, r0, r1, lsl #8
|
||||
; CHECK-ARMv6-NEXT: bx lr
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc < %s -mtriple=arm-unknown | FileCheck %s
|
||||
; RUN: llc < %s -mtriple=armv6-unknown | FileCheck %s --check-prefix=CHECK-ARMv6
|
||||
|
||||
@ -5,20 +6,27 @@
|
||||
; (i32) p[0] | ((i32) p[1] << 8) | ((i32) p[2] << 16) | ((i32) p[3] << 24)
|
||||
define i32 @load_i32_by_i8_unaligned(i32* %arg) {
|
||||
; CHECK-LABEL: load_i32_by_i8_unaligned:
|
||||
; CHECK: ldrb{{.*}}r0
|
||||
; CHECK: ldrb{{.*}}r0
|
||||
; CHECK: ldrb{{.*}}r0
|
||||
; CHECK: ldrb{{.*}}r0
|
||||
; CHECK: orr
|
||||
; CHECK: mov pc, lr
|
||||
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: ldrb r2, [r0, #1]
|
||||
; CHECK-NEXT: ldrb r1, [r0]
|
||||
; CHECK-NEXT: ldrb r3, [r0, #2]
|
||||
; CHECK-NEXT: ldrb r0, [r0, #3]
|
||||
; CHECK-NEXT: orr r1, r1, r2, lsl #8
|
||||
; CHECK-NEXT: orr r1, r1, r3, lsl #16
|
||||
; CHECK-NEXT: orr r0, r1, r0, lsl #24
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
;
|
||||
; CHECK-ARMv6-LABEL: load_i32_by_i8_unaligned:
|
||||
; CHECK-ARMv6: ldrb{{.*}}r0
|
||||
; CHECK-ARMv6: ldrb{{.*}}r0
|
||||
; CHECK-ARMv6: ldrb{{.*}}r0
|
||||
; CHECK-ARMv6: ldrb{{.*}}r0
|
||||
; CHECK-ARMv6: orr
|
||||
; CHECK-ARMv6: bx lr
|
||||
; CHECK-ARMv6: @ %bb.0:
|
||||
; CHECK-ARMv6-NEXT: ldrb r2, [r0, #1]
|
||||
; CHECK-ARMv6-NEXT: ldrb r1, [r0]
|
||||
; CHECK-ARMv6-NEXT: ldrb r3, [r0, #2]
|
||||
; CHECK-ARMv6-NEXT: ldrb r0, [r0, #3]
|
||||
; CHECK-ARMv6-NEXT: orr r1, r1, r2, lsl #8
|
||||
; CHECK-ARMv6-NEXT: orr r1, r1, r3, lsl #16
|
||||
; CHECK-ARMv6-NEXT: orr r0, r1, r0, lsl #24
|
||||
; CHECK-ARMv6-NEXT: bx lr
|
||||
|
||||
%tmp = bitcast i32* %arg to i8*
|
||||
%tmp1 = getelementptr inbounds i8, i8* %tmp, i32 0
|
||||
%tmp2 = load i8, i8* %tmp1, align 1
|
||||
@ -45,12 +53,15 @@ define i32 @load_i32_by_i8_unaligned(i32* %arg) {
|
||||
; (i32) p[0] | ((i32) p[1] << 8) | ((i32) p[2] << 16) | ((i32) p[3] << 24)
|
||||
define i32 @load_i32_by_i8_aligned(i32* %arg) {
|
||||
; CHECK-LABEL: load_i32_by_i8_aligned:
|
||||
; CHECK: ldr r0, [r0]
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: ldr r0, [r0]
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
|
||||
;
|
||||
; CHECK-ARMv6-LABEL: load_i32_by_i8_aligned:
|
||||
; CHECK-ARMv6: ldr r0, [r0]
|
||||
; CHECK-ARMv6: @ %bb.0:
|
||||
; CHECK-ARMv6-NEXT: ldr r0, [r0]
|
||||
; CHECK-ARMv6-NEXT: bx lr
|
||||
|
||||
%tmp = bitcast i32* %arg to i8*
|
||||
%tmp1 = getelementptr inbounds i8, i8* %tmp, i32 0
|
||||
%tmp2 = load i8, i8* %tmp1, align 4
|
||||
@ -78,18 +89,23 @@ define i32 @load_i32_by_i8_aligned(i32* %arg) {
|
||||
define i32 @load_i32_by_i8_bswap(i32* %arg) {
|
||||
; BSWAP is not supported by 32 bit target
|
||||
; CHECK-LABEL: load_i32_by_i8_bswap:
|
||||
; CHECK: ldr r0, [r0]
|
||||
; CHECK: and
|
||||
; CHECK-NEXT: and
|
||||
; CHECK-NEXT: orr
|
||||
; CHECK-NEXT: orr
|
||||
; CHECK-NEXT: orr
|
||||
; CHECK: mov pc, lr
|
||||
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: ldr r0, [r0]
|
||||
; CHECK-NEXT: mov r1, #65280
|
||||
; CHECK-NEXT: mov r2, #16711680
|
||||
; CHECK-NEXT: and r1, r1, r0, lsr #8
|
||||
; CHECK-NEXT: and r2, r2, r0, lsl #8
|
||||
; CHECK-NEXT: orr r1, r1, r0, lsr #24
|
||||
; CHECK-NEXT: orr r0, r2, r0, lsl #24
|
||||
; CHECK-NEXT: orr r0, r0, r1
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
;
|
||||
; CHECK-ARMv6-LABEL: load_i32_by_i8_bswap:
|
||||
; CHECK-ARMv6: ldr r0, [r0]
|
||||
; CHECK-ARMv6: @ %bb.0:
|
||||
; CHECK-ARMv6-NEXT: ldr r0, [r0]
|
||||
; CHECK-ARMv6-NEXT: rev r0, r0
|
||||
; CHECK-ARMv6-NEXT: bx lr
|
||||
|
||||
%tmp = bitcast i32* %arg to i8*
|
||||
%tmp1 = load i8, i8* %tmp, align 4
|
||||
%tmp2 = zext i8 %tmp1 to i32
|
||||
@ -115,14 +131,17 @@ define i32 @load_i32_by_i8_bswap(i32* %arg) {
|
||||
; (i64) p[0] | ((i64) p[1] << 8) | ((i64) p[2] << 16) | ((i64) p[3] << 24) | ((i64) p[4] << 32) | ((i64) p[5] << 40) | ((i64) p[6] << 48) | ((i64) p[7] << 56)
|
||||
define i64 @load_i64_by_i8(i64* %arg) {
|
||||
; CHECK-LABEL: load_i64_by_i8:
|
||||
; CHECK: ldr r2, [r0]
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: ldr r2, [r0]
|
||||
; CHECK-NEXT: ldr r1, [r0, #4]
|
||||
; CHECK-NEXT: mov r0, r2
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
|
||||
;
|
||||
; CHECK-ARMv6-LABEL: load_i64_by_i8:
|
||||
; CHECK-ARMv6: ldrd r0, r1, [r0]
|
||||
; CHECK-ARMv6: bx lr
|
||||
; CHECK-ARMv6: @ %bb.0:
|
||||
; CHECK-ARMv6-NEXT: ldrd r0, r1, [r0]
|
||||
; CHECK-ARMv6-NEXT: bx lr
|
||||
|
||||
%tmp = bitcast i64* %arg to i8*
|
||||
%tmp1 = load i8, i8* %tmp, align 8
|
||||
%tmp2 = zext i8 %tmp1 to i64
|
||||
@ -168,25 +187,32 @@ define i64 @load_i64_by_i8(i64* %arg) {
|
||||
; ((i64) p[0] << 56) | ((i64) p[1] << 48) | ((i64) p[2] << 40) | ((i64) p[3] << 32) | ((i64) p[4] << 24) | ((i64) p[5] << 16) | ((i64) p[6] << 8) | (i64) p[7]
|
||||
define i64 @load_i64_by_i8_bswap(i64* %arg) {
|
||||
; CHECK-LABEL: load_i64_by_i8_bswap:
|
||||
; CHECK: ldr{{.*}}r0
|
||||
; CHECK: ldr{{.*}}r0
|
||||
; CHECK: and
|
||||
; CHECK-NEXT: and
|
||||
; CHECK-NEXT: orr
|
||||
; CHECK-NEXT: orr
|
||||
; CHECK-NEXT: and
|
||||
; CHECK-NEXT: orr
|
||||
; CHECK-NEXT: and
|
||||
; CHECK-NEXT: orr
|
||||
; CHECK-NEXT: orr
|
||||
; CHECK-NEXT: orr
|
||||
; CHECK: mov pc, lr
|
||||
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: push {r11, lr}
|
||||
; CHECK-NEXT: ldr r1, [r0]
|
||||
; CHECK-NEXT: mov r12, #65280
|
||||
; CHECK-NEXT: ldr r0, [r0, #4]
|
||||
; CHECK-NEXT: mov lr, #16711680
|
||||
; CHECK-NEXT: and r3, r12, r0, lsr #8
|
||||
; CHECK-NEXT: and r2, lr, r0, lsl #8
|
||||
; CHECK-NEXT: orr r3, r3, r0, lsr #24
|
||||
; CHECK-NEXT: orr r0, r2, r0, lsl #24
|
||||
; CHECK-NEXT: and r2, r12, r1, lsr #8
|
||||
; CHECK-NEXT: orr r0, r0, r3
|
||||
; CHECK-NEXT: and r3, lr, r1, lsl #8
|
||||
; CHECK-NEXT: orr r2, r2, r1, lsr #24
|
||||
; CHECK-NEXT: orr r1, r3, r1, lsl #24
|
||||
; CHECK-NEXT: orr r1, r1, r2
|
||||
; CHECK-NEXT: pop {r11, lr}
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
;
|
||||
; CHECK-ARMv6-LABEL: load_i64_by_i8_bswap:
|
||||
; CHECK-ARMv6: ldrd r2, r3, [r0]
|
||||
; CHECK-ARMv6: rev r0, r3
|
||||
; CHECK-ARMv6: rev r1, r2
|
||||
; CHECK-ARMv6: bx lr
|
||||
; CHECK-ARMv6: @ %bb.0:
|
||||
; CHECK-ARMv6-NEXT: ldrd r2, r3, [r0]
|
||||
; CHECK-ARMv6-NEXT: rev r0, r3
|
||||
; CHECK-ARMv6-NEXT: rev r1, r2
|
||||
; CHECK-ARMv6-NEXT: bx lr
|
||||
|
||||
%tmp = bitcast i64* %arg to i8*
|
||||
%tmp1 = load i8, i8* %tmp, align 8
|
||||
%tmp2 = zext i8 %tmp1 to i64
|
||||
@ -232,13 +258,16 @@ define i64 @load_i64_by_i8_bswap(i64* %arg) {
|
||||
; (i32) p[1] | ((i32) p[2] << 8) | ((i32) p[3] << 16) | ((i32) p[4] << 24)
|
||||
define i32 @load_i32_by_i8_nonzero_offset(i32* %arg) {
|
||||
; CHECK-LABEL: load_i32_by_i8_nonzero_offset:
|
||||
; CHECK: ldr r0, [r0, #1]
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: ldr r0, [r0, #1]
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
|
||||
;
|
||||
; CHECK-ARMv6-LABEL: load_i32_by_i8_nonzero_offset:
|
||||
; CHECK-ARMv6: ldr r0, [r0, #1]
|
||||
; CHECK-ARMv6: @ %bb.0:
|
||||
; CHECK-ARMv6-NEXT: ldr r0, [r0, #1]
|
||||
; CHECK-ARMv6-NEXT: bx lr
|
||||
|
||||
|
||||
%tmp = bitcast i32* %arg to i8*
|
||||
%tmp1 = getelementptr inbounds i8, i8* %tmp, i32 1
|
||||
%tmp2 = load i8, i8* %tmp1, align 4
|
||||
@ -265,13 +294,16 @@ define i32 @load_i32_by_i8_nonzero_offset(i32* %arg) {
|
||||
; (i32) p[-4] | ((i32) p[-3] << 8) | ((i32) p[-2] << 16) | ((i32) p[-1] << 24)
|
||||
define i32 @load_i32_by_i8_neg_offset(i32* %arg) {
|
||||
; CHECK-LABEL: load_i32_by_i8_neg_offset:
|
||||
; CHECK: ldr r0, [r0, #-4]
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: ldr r0, [r0, #-4]
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
|
||||
;
|
||||
; CHECK-ARMv6-LABEL: load_i32_by_i8_neg_offset:
|
||||
; CHECK-ARMv6: ldr r0, [r0, #-4]
|
||||
; CHECK-ARMv6: @ %bb.0:
|
||||
; CHECK-ARMv6-NEXT: ldr r0, [r0, #-4]
|
||||
; CHECK-ARMv6-NEXT: bx lr
|
||||
|
||||
|
||||
%tmp = bitcast i32* %arg to i8*
|
||||
%tmp1 = getelementptr inbounds i8, i8* %tmp, i32 -4
|
||||
%tmp2 = load i8, i8* %tmp1, align 4
|
||||
@ -298,7 +330,8 @@ define i32 @load_i32_by_i8_neg_offset(i32* %arg) {
|
||||
; (i32) p[4] | ((i32) p[3] << 8) | ((i32) p[2] << 16) | ((i32) p[1] << 24)
|
||||
define i32 @load_i32_by_i8_nonzero_offset_bswap(i32* %arg) {
|
||||
; CHECK-LABEL: load_i32_by_i8_nonzero_offset_bswap:
|
||||
; CHECK: ldr r0, [r0, #1]
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: ldr r0, [r0, #1]
|
||||
; CHECK-NEXT: mov r1, #65280
|
||||
; CHECK-NEXT: mov r2, #16711680
|
||||
; CHECK-NEXT: and r1, r1, r0, lsr #8
|
||||
@ -307,12 +340,14 @@ define i32 @load_i32_by_i8_nonzero_offset_bswap(i32* %arg) {
|
||||
; CHECK-NEXT: orr r0, r2, r0, lsl #24
|
||||
; CHECK-NEXT: orr r0, r0, r1
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
|
||||
;
|
||||
; CHECK-ARMv6-LABEL: load_i32_by_i8_nonzero_offset_bswap:
|
||||
; CHECK-ARMv6: ldr r0, [r0, #1]
|
||||
; CHECK-ARMv6: @ %bb.0:
|
||||
; CHECK-ARMv6-NEXT: ldr r0, [r0, #1]
|
||||
; CHECK-ARMv6-NEXT: rev r0, r0
|
||||
; CHECK-ARMv6-NEXT: bx lr
|
||||
|
||||
|
||||
%tmp = bitcast i32* %arg to i8*
|
||||
%tmp1 = getelementptr inbounds i8, i8* %tmp, i32 4
|
||||
%tmp2 = load i8, i8* %tmp1, align 1
|
||||
@ -339,7 +374,8 @@ define i32 @load_i32_by_i8_nonzero_offset_bswap(i32* %arg) {
|
||||
; (i32) p[-1] | ((i32) p[-2] << 8) | ((i32) p[-3] << 16) | ((i32) p[-4] << 24)
|
||||
define i32 @load_i32_by_i8_neg_offset_bswap(i32* %arg) {
|
||||
; CHECK-LABEL: load_i32_by_i8_neg_offset_bswap:
|
||||
; CHECK: ldr r0, [r0, #-4]
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: ldr r0, [r0, #-4]
|
||||
; CHECK-NEXT: mov r1, #65280
|
||||
; CHECK-NEXT: mov r2, #16711680
|
||||
; CHECK-NEXT: and r1, r1, r0, lsr #8
|
||||
@ -348,12 +384,14 @@ define i32 @load_i32_by_i8_neg_offset_bswap(i32* %arg) {
|
||||
; CHECK-NEXT: orr r0, r2, r0, lsl #24
|
||||
; CHECK-NEXT: orr r0, r0, r1
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
|
||||
;
|
||||
; CHECK-ARMv6-LABEL: load_i32_by_i8_neg_offset_bswap:
|
||||
; CHECK-ARMv6: ldr r0, [r0, #-4]
|
||||
; CHECK-ARMv6: @ %bb.0:
|
||||
; CHECK-ARMv6-NEXT: ldr r0, [r0, #-4]
|
||||
; CHECK-ARMv6-NEXT: rev r0, r0
|
||||
; CHECK-ARMv6-NEXT: bx lr
|
||||
|
||||
|
||||
%tmp = bitcast i32* %arg to i8*
|
||||
%tmp1 = getelementptr inbounds i8, i8* %tmp, i32 -1
|
||||
%tmp2 = load i8, i8* %tmp1, align 1
|
||||
@ -382,7 +420,8 @@ declare i16 @llvm.bswap.i16(i16)
|
||||
; (i32) bswap(p[1]) | (i32) bswap(p[0] << 16)
|
||||
define i32 @load_i32_by_bswap_i16(i32* %arg) {
|
||||
; CHECK-LABEL: load_i32_by_bswap_i16:
|
||||
; CHECK: ldr r0, [r0]
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: ldr r0, [r0]
|
||||
; CHECK-NEXT: mov r1, #65280
|
||||
; CHECK-NEXT: mov r2, #16711680
|
||||
; CHECK-NEXT: and r1, r1, r0, lsr #8
|
||||
@ -391,12 +430,14 @@ define i32 @load_i32_by_bswap_i16(i32* %arg) {
|
||||
; CHECK-NEXT: orr r0, r2, r0, lsl #24
|
||||
; CHECK-NEXT: orr r0, r0, r1
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
|
||||
;
|
||||
; CHECK-ARMv6-LABEL: load_i32_by_bswap_i16:
|
||||
; CHECK-ARMv6: ldr r0, [r0]
|
||||
; CHECK-ARMv6: @ %bb.0:
|
||||
; CHECK-ARMv6-NEXT: ldr r0, [r0]
|
||||
; CHECK-ARMv6-NEXT: rev r0, r0
|
||||
; CHECK-ARMv6-NEXT: bx lr
|
||||
|
||||
|
||||
%tmp = bitcast i32* %arg to i16*
|
||||
%tmp1 = load i16, i16* %tmp, align 4
|
||||
%tmp11 = call i16 @llvm.bswap.i16(i16 %tmp1)
|
||||
@ -414,11 +455,13 @@ define i32 @load_i32_by_bswap_i16(i32* %arg) {
|
||||
; (i32) p[0] | (sext(p[1] << 16) to i32)
|
||||
define i32 @load_i32_by_sext_i16(i32* %arg) {
|
||||
; CHECK-LABEL: load_i32_by_sext_i16:
|
||||
; CHECK: ldr r0, [r0]
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: ldr r0, [r0]
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
;
|
||||
; CHECK-ARMv6-LABEL: load_i32_by_sext_i16:
|
||||
; CHECK-ARMv6: ldr r0, [r0]
|
||||
; CHECK-ARMv6: @ %bb.0:
|
||||
; CHECK-ARMv6-NEXT: ldr r0, [r0]
|
||||
; CHECK-ARMv6-NEXT: bx lr
|
||||
%tmp = bitcast i32* %arg to i16*
|
||||
%tmp1 = load i16, i16* %tmp, align 4
|
||||
@ -436,12 +479,14 @@ define i32 @load_i32_by_sext_i16(i32* %arg) {
|
||||
; (i32) p[i] | ((i32) p[i + 1] << 8) | ((i32) p[i + 2] << 16) | ((i32) p[i + 3] << 24)
|
||||
define i32 @load_i32_by_i8_base_offset_index(i8* %arg, i32 %i) {
|
||||
; CHECK-LABEL: load_i32_by_i8_base_offset_index:
|
||||
; CHECK: add r0, r0, r1
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: add r0, r0, r1
|
||||
; CHECK-NEXT: ldr r0, [r0, #12]
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
;
|
||||
; CHECK-ARMv6-LABEL: load_i32_by_i8_base_offset_index:
|
||||
; CHECK-ARMv6: add r0, r0, r1
|
||||
; CHECK-ARMv6: @ %bb.0:
|
||||
; CHECK-ARMv6-NEXT: add r0, r0, r1
|
||||
; CHECK-ARMv6-NEXT: ldr r0, [r0, #12]
|
||||
; CHECK-ARMv6-NEXT: bx lr
|
||||
|
||||
@ -479,12 +524,14 @@ define i32 @load_i32_by_i8_base_offset_index(i8* %arg, i32 %i) {
|
||||
; (i32) p[i + 1] | ((i32) p[i + 2] << 8) | ((i32) p[i + 3] << 16) | ((i32) p[i + 4] << 24)
|
||||
define i32 @load_i32_by_i8_base_offset_index_2(i8* %arg, i32 %i) {
|
||||
; CHECK-LABEL: load_i32_by_i8_base_offset_index_2:
|
||||
; CHECK: add r0, r1, r0
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: add r0, r1, r0
|
||||
; CHECK-NEXT: ldr r0, [r0, #13]
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
;
|
||||
; CHECK-ARMv6-LABEL: load_i32_by_i8_base_offset_index_2:
|
||||
; CHECK-ARMv6: add r0, r1, r0
|
||||
; CHECK-ARMv6: @ %bb.0:
|
||||
; CHECK-ARMv6-NEXT: add r0, r1, r0
|
||||
; CHECK-ARMv6-NEXT: ldr r0, [r0, #13]
|
||||
; CHECK-ARMv6-NEXT: bx lr
|
||||
%tmp = add nuw nsw i32 %i, 4
|
||||
@ -521,13 +568,15 @@ define i32 @load_i32_by_i8_base_offset_index_2(i8* %arg, i32 %i) {
|
||||
; (i32) p[0] | ((i32) p[1] << 8)
|
||||
define i32 @zext_load_i32_by_i8(i32* %arg) {
|
||||
; CHECK-LABEL: zext_load_i32_by_i8:
|
||||
; CHECK: ldrb r1, [r0]
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: ldrb r1, [r0]
|
||||
; CHECK-NEXT: ldrb r0, [r0, #1]
|
||||
; CHECK-NEXT: orr r0, r1, r0, lsl #8
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
;
|
||||
; CHECK-ARMv6-LABEL: zext_load_i32_by_i8:
|
||||
; CHECK-ARMv6: ldrb r1, [r0]
|
||||
; CHECK-ARMv6: @ %bb.0:
|
||||
; CHECK-ARMv6-NEXT: ldrb r1, [r0]
|
||||
; CHECK-ARMv6-NEXT: ldrb r0, [r0, #1]
|
||||
; CHECK-ARMv6-NEXT: orr r0, r1, r0, lsl #8
|
||||
; CHECK-ARMv6-NEXT: bx lr
|
||||
@ -548,14 +597,16 @@ define i32 @zext_load_i32_by_i8(i32* %arg) {
|
||||
; ((i32) p[0] << 8) | ((i32) p[1] << 16)
|
||||
define i32 @zext_load_i32_by_i8_shl_8(i32* %arg) {
|
||||
; CHECK-LABEL: zext_load_i32_by_i8_shl_8:
|
||||
; CHECK: ldrb r1, [r0]
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: ldrb r1, [r0]
|
||||
; CHECK-NEXT: ldrb r0, [r0, #1]
|
||||
; CHECK-NEXT: lsl r0, r0, #16
|
||||
; CHECK-NEXT: orr r0, r0, r1, lsl #8
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
;
|
||||
; CHECK-ARMv6-LABEL: zext_load_i32_by_i8_shl_8:
|
||||
; CHECK-ARMv6: ldrb r1, [r0]
|
||||
; CHECK-ARMv6: @ %bb.0:
|
||||
; CHECK-ARMv6-NEXT: ldrb r1, [r0]
|
||||
; CHECK-ARMv6-NEXT: ldrb r0, [r0, #1]
|
||||
; CHECK-ARMv6-NEXT: lsl r0, r0, #16
|
||||
; CHECK-ARMv6-NEXT: orr r0, r0, r1, lsl #8
|
||||
@ -578,14 +629,16 @@ define i32 @zext_load_i32_by_i8_shl_8(i32* %arg) {
|
||||
; ((i32) p[0] << 16) | ((i32) p[1] << 24)
|
||||
define i32 @zext_load_i32_by_i8_shl_16(i32* %arg) {
|
||||
; CHECK-LABEL: zext_load_i32_by_i8_shl_16:
|
||||
; CHECK: ldrb r1, [r0]
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: ldrb r1, [r0]
|
||||
; CHECK-NEXT: ldrb r0, [r0, #1]
|
||||
; CHECK-NEXT: lsl r0, r0, #24
|
||||
; CHECK-NEXT: orr r0, r0, r1, lsl #16
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
;
|
||||
; CHECK-ARMv6-LABEL: zext_load_i32_by_i8_shl_16:
|
||||
; CHECK-ARMv6: ldrb r1, [r0]
|
||||
; CHECK-ARMv6: @ %bb.0:
|
||||
; CHECK-ARMv6-NEXT: ldrb r1, [r0]
|
||||
; CHECK-ARMv6-NEXT: ldrb r0, [r0, #1]
|
||||
; CHECK-ARMv6-NEXT: lsl r0, r0, #24
|
||||
; CHECK-ARMv6-NEXT: orr r0, r0, r1, lsl #16
|
||||
@ -608,13 +661,15 @@ define i32 @zext_load_i32_by_i8_shl_16(i32* %arg) {
|
||||
; (i32) p[1] | ((i32) p[0] << 8)
|
||||
define i32 @zext_load_i32_by_i8_bswap(i32* %arg) {
|
||||
; CHECK-LABEL: zext_load_i32_by_i8_bswap:
|
||||
; CHECK: ldrb r1, [r0]
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: ldrb r1, [r0]
|
||||
; CHECK-NEXT: ldrb r0, [r0, #1]
|
||||
; CHECK-NEXT: orr r0, r0, r1, lsl #8
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
;
|
||||
; CHECK-ARMv6-LABEL: zext_load_i32_by_i8_bswap:
|
||||
; CHECK-ARMv6: ldrb r1, [r0]
|
||||
; CHECK-ARMv6: @ %bb.0:
|
||||
; CHECK-ARMv6-NEXT: ldrb r1, [r0]
|
||||
; CHECK-ARMv6-NEXT: ldrb r0, [r0, #1]
|
||||
; CHECK-ARMv6-NEXT: orr r0, r0, r1, lsl #8
|
||||
; CHECK-ARMv6-NEXT: bx lr
|
||||
@ -635,14 +690,16 @@ define i32 @zext_load_i32_by_i8_bswap(i32* %arg) {
|
||||
; ((i32) p[1] << 8) | ((i32) p[0] << 16)
|
||||
define i32 @zext_load_i32_by_i8_bswap_shl_8(i32* %arg) {
|
||||
; CHECK-LABEL: zext_load_i32_by_i8_bswap_shl_8:
|
||||
; CHECK: ldrb r1, [r0]
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: ldrb r1, [r0]
|
||||
; CHECK-NEXT: ldrb r0, [r0, #1]
|
||||
; CHECK-NEXT: lsl r1, r1, #16
|
||||
; CHECK-NEXT: orr r0, r1, r0, lsl #8
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
;
|
||||
; CHECK-ARMv6-LABEL: zext_load_i32_by_i8_bswap_shl_8:
|
||||
; CHECK-ARMv6: ldrb r1, [r0]
|
||||
; CHECK-ARMv6: @ %bb.0:
|
||||
; CHECK-ARMv6-NEXT: ldrb r1, [r0]
|
||||
; CHECK-ARMv6-NEXT: ldrb r0, [r0, #1]
|
||||
; CHECK-ARMv6-NEXT: lsl r1, r1, #16
|
||||
; CHECK-ARMv6-NEXT: orr r0, r1, r0, lsl #8
|
||||
@ -665,14 +722,16 @@ define i32 @zext_load_i32_by_i8_bswap_shl_8(i32* %arg) {
|
||||
; ((i32) p[1] << 16) | ((i32) p[0] << 24)
|
||||
define i32 @zext_load_i32_by_i8_bswap_shl_16(i32* %arg) {
|
||||
; CHECK-LABEL: zext_load_i32_by_i8_bswap_shl_16:
|
||||
; CHECK: ldrb r1, [r0]
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: ldrb r1, [r0]
|
||||
; CHECK-NEXT: ldrb r0, [r0, #1]
|
||||
; CHECK-NEXT: lsl r1, r1, #24
|
||||
; CHECK-NEXT: orr r0, r1, r0, lsl #16
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
;
|
||||
; CHECK-ARMv6-LABEL: zext_load_i32_by_i8_bswap_shl_16:
|
||||
; CHECK-ARMv6: ldrb r1, [r0]
|
||||
; CHECK-ARMv6: @ %bb.0:
|
||||
; CHECK-ARMv6-NEXT: ldrb r1, [r0]
|
||||
; CHECK-ARMv6-NEXT: ldrb r0, [r0, #1]
|
||||
; CHECK-ARMv6-NEXT: lsl r1, r1, #24
|
||||
; CHECK-ARMv6-NEXT: orr r0, r1, r0, lsl #16
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user