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[ARM] Support inline assembler constraints for MVE.
"To" selects an odd-numbered GPR, and "Te" an even one. There are some 8.1-M instructions that have one too few bits in their register fields and require registers of particular parity, without necessarily using a consecutive even/odd pair. Also, the constraint letter "t" should select an MVE q-register, when MVE is present. This didn't need any source changes, but some extra tests have been added. Reviewers: dmgreen, samparker, SjoerdMeijer Subscribers: javed.absar, eraman, kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D60709 llvm-svn: 364331
This commit is contained in:
Simon Tatham
parent
6dccf8a815
commit
e89f971e45
@ -3795,6 +3795,8 @@ All ARM modes:
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- ``Q``, ``Um``, ``Un``, ``Uq``, ``Us``, ``Ut``, ``Uv``, ``Uy``: Memory address
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operand. Treated the same as operand ``m``, at the moment.
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- ``Te``: An even general-purpose 32-bit integer register: ``r0,r2,...,r12,r14``
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- ``To``: An odd general-purpose 32-bit integer register: ``r1,r3,...,r11``
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ARM and ARM's Thumb2 mode:
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@ -14002,6 +14002,7 @@ ARMTargetLowering::getConstraintType(StringRef Constraint) const {
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} else if (Constraint.size() == 2) {
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switch (Constraint[0]) {
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default: break;
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case 'T': return C_RegisterClass;
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// All 'U+' constraints are addresses.
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case 'U': return C_Memory;
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}
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@ -14047,7 +14048,8 @@ using RCPair = std::pair<unsigned, const TargetRegisterClass *>;
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RCPair ARMTargetLowering::getRegForInlineAsmConstraint(
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const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
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if (Constraint.size() == 1) {
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switch (Constraint.size()) {
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case 1:
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// GCC ARM Constraint Letters
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switch (Constraint[0]) {
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case 'l': // Low regs or general regs.
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@ -14093,7 +14095,26 @@ RCPair ARMTargetLowering::getRegForInlineAsmConstraint(
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return RCPair(0U, &ARM::QPR_VFP2RegClass);
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break;
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}
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case 2:
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switch (Constraint[0]) {
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case 'T':
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switch (Constraint[1]) {
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default:
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break;
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case 'e':
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return RCPair(0U, &ARM::tGPREvenRegClass);
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case 'o':
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return RCPair(0U, &ARM::tGPROddRegClass);
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}
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default:
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break;
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}
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default:
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break;
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}
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if (StringRef("{cc}").equals_lower(Constraint))
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return std::make_pair(unsigned(ARM::CPSR), &ARM::CCRRegClass);
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@ -48,3 +48,27 @@ entry:
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%0 = tail call <4 x float> asm "vadd.f32 $0, $1, $2", "=t,t,t"(<4 x float> %a, <4 x float> %b)
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ret <4 x float> %0
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}
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define i32 @even-GPR-constraint() {
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entry:
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; CHECK-LABEL: even-GPR-constraint
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; CHECK: add [[REG:r1*[0, 2, 4, 6, 8]]], [[REG]], #1
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; CHECK: add [[REG:r1*[0, 2, 4, 6, 8]]], [[REG]], #2
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; CHECK: add [[REG:r1*[0, 2, 4, 6, 8]]], [[REG]], #3
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; CHECK: add [[REG:r1*[0, 2, 4, 6, 8]]], [[REG]], #4
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%0 = tail call { i32, i32, i32, i32 } asm "add $0, #1\0Aadd $1, #2\0Aadd $2, #3\0Aadd $3, #4\0A", "=^Te,=^Te,=^Te,=^Te,0,1,2,3"(i32 0, i32 0, i32 0, i32 0)
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%asmresult = extractvalue { i32, i32, i32, i32 } %0, 0
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ret i32 %asmresult
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}
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define i32 @odd-GPR-constraint() {
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entry:
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; CHECK-LABEL: odd-GPR-constraint
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; CHECK: add [[REG:r1*[1, 3, 5, 7, 9]]], [[REG]], #1
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; CHECK: add [[REG:r1*[1, 3, 5, 7, 9]]], [[REG]], #2
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; CHECK: add [[REG:r1*[1, 3, 5, 7, 9]]], [[REG]], #3
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; CHECK: add [[REG:r1*[1, 3, 5, 7, 9]]], [[REG]], #4
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%0 = tail call { i32, i32, i32, i32 } asm "add $0, #1\0Aadd $1, #2\0Aadd $2, #3\0Aadd $3, #4\0A", "=^To,=^To,=^To,=^To,0,1,2,3"(i32 0, i32 0, i32 0, i32 0)
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%asmresult = extractvalue { i32, i32, i32, i32 } %0, 0
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ret i32 %asmresult
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}
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14
test/CodeGen/Thumb2/inlineasm-error-t-toofewregs-mve.ll
Normal file
14
test/CodeGen/Thumb2/inlineasm-error-t-toofewregs-mve.ll
Normal file
@ -0,0 +1,14 @@
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; RUN: not llc -mtriple=armv8.1-m-eabi -mattr=+mve %s -o /dev/null 2>&1 | FileCheck %s
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; CHECK: inline assembly requires more registers than available
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define arm_aapcs_vfpcc <4 x i32> @t-constraint-i32-vectors-too-few-regs(<4 x i32> %a, <4 x i32> %b) {
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entry:
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%0 = tail call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>,
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<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> }
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asm "",
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"=t,=t,=t,=t,=t,=t,=t,=t,=t,=t,t,t"(<4 x i32> %a, <4 x i32> %b)
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%asmresult = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>,
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<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>,
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<4 x i32>, <4 x i32> } %0, 0
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ret <4 x i32> %asmresult
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}
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48
test/CodeGen/Thumb2/inlineasm-mve.ll
Normal file
48
test/CodeGen/Thumb2/inlineasm-mve.ll
Normal file
@ -0,0 +1,48 @@
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; RUN: llc -mtriple=armv8.1-m-eabi -mattr=+mve %s -o - | FileCheck %s
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define i32 @test1(i32 %tmp54) {
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%tmp56 = tail call i32 asm "uxtb16 $0,$1", "=r,r"( i32 %tmp54 )
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ret i32 %tmp56
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}
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define void @test2() {
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tail call void asm sideeffect "/* number: ${0:c} */", "i"( i32 1 )
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ret void
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}
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define arm_aapcs_vfpcc <4 x i32> @mve-t-constraint-128bit(<4 x i32>, <4 x i32>) {
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; CHECK-LABEL: mve-t-constraint-128bit
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; CHECK: vadd.i32 q{{[0-7]}}, q{{[0-7]}}, q{{[0-7]}}
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%ret = tail call <4 x i32>
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asm "vadd.i32 $0, $1, $2", "=t,t,t"
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(<4 x i32> %0, <4 x i32> %1)
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ret <4 x i32> %ret
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}
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define i32 @even-GPR-constraint() {
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entry:
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; CHECK-LABEL: even-GPR-constraint
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; CHECK: add [[REG:r1*[0, 2, 4, 6, 8]]], [[REG]], #1
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; CHECK: add [[REG:r1*[0, 2, 4, 6, 8]]], [[REG]], #2
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; CHECK: add [[REG:r1*[0, 2, 4, 6, 8]]], [[REG]], #3
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; CHECK: add [[REG:r1*[0, 2, 4, 6, 8]]], [[REG]], #4
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%0 = tail call { i32, i32, i32, i32 }
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asm "add $0, #1\0Aadd $1, #2\0Aadd $2, #3\0Aadd $3, #4\0A", "=^Te,=^Te,=^Te,=^Te,0,1,2,3"
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(i32 0, i32 0, i32 0, i32 0)
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%asmresult = extractvalue { i32, i32, i32, i32 } %0, 0
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ret i32 %asmresult
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}
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define i32 @odd-GPR-constraint() {
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entry:
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; CHECK-LABEL: odd-GPR-constraint
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; CHECK: add [[REG:r1*[1, 3, 5, 7, 9]]], [[REG]], #1
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; CHECK: add [[REG:r1*[1, 3, 5, 7, 9]]], [[REG]], #2
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; CHECK: add [[REG:r1*[1, 3, 5, 7, 9]]], [[REG]], #3
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; CHECK: add [[REG:r1*[1, 3, 5, 7, 9]]], [[REG]], #4
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%0 = tail call { i32, i32, i32, i32 }
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asm "add $0, #1\0Aadd $1, #2\0Aadd $2, #3\0Aadd $3, #4\0A", "=^To,=^To,=^To,=^To,0,1,2,3"
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(i32 0, i32 0, i32 0, i32 0)
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%asmresult = extractvalue { i32, i32, i32, i32 } %0, 0
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ret i32 %asmresult
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}
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