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https://github.com/RPCS3/llvm-mirror.git
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[Hexagon] Implement buildVector32 and buildVector64 as utility functions
Change LowerBUILD_VECTOR to use those functions. This commit will tempora- rily affect constant vector generation (it will generate constant-extended values instead of non-extended combines), but the code for the general case should be better. The constant selection part will be fixed later. llvm-svn: 318877
This commit is contained in:
Krzysztof Parzyszek
parent
2a2b3cd66d
commit
e8d084d3f2
@ -2461,151 +2461,159 @@ HexagonTargetLowering::LowerVECTOR_SHIFT(SDValue Op, SelectionDAG &DAG) const {
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}
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SDValue
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HexagonTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
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BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
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SDLoc dl(Op);
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EVT VT = Op.getValueType();
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HexagonTargetLowering::buildVector32(ArrayRef<SDValue> Elem, const SDLoc &dl,
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MVT VecTy, SelectionDAG &DAG) const {
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MVT ElemTy = VecTy.getVectorElementType();
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assert(VecTy.getVectorNumElements() == Elem.size());
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unsigned Size = VT.getSizeInBits();
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SmallVector<ConstantSDNode*,4> Consts;
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bool AllConst = true;
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for (SDValue V : Elem) {
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if (V.getOpcode() == ISD::UNDEF)
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V = DAG.getConstant(0, dl, ElemTy);
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auto *C = dyn_cast<ConstantSDNode>(V.getNode());
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Consts.push_back(C);
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AllConst = AllConst && C != nullptr;
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}
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// Only handle vectors of 64 bits or shorter.
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if (Size > 64)
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return SDValue();
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unsigned First, Num = Elem.size();
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for (First = 0; First != Num; ++First)
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if (Elem[First].getOpcode() != ISD::UNDEF)
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break;
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if (First == Num)
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return DAG.getUNDEF(VecTy);
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unsigned NElts = BVN->getNumOperands();
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// Try to generate a SPLAT instruction.
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if (VT == MVT::v4i8 || VT == MVT::v4i16 || VT == MVT::v2i32) {
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APInt APSplatBits, APSplatUndef;
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unsigned SplatBitSize;
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bool HasAnyUndefs;
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if (BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
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HasAnyUndefs, 0, false)) {
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if (SplatBitSize == VT.getVectorElementType().getSizeInBits()) {
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unsigned ZV = APSplatBits.getZExtValue();
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assert(SplatBitSize <= 32 && "Can only handle up to i32");
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// Sign-extend the splat value from SplatBitSize to 32.
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int32_t SV = SplatBitSize < 32
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? int32_t(ZV << (32-SplatBitSize)) >> (32-SplatBitSize)
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: int32_t(ZV);
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return DAG.getNode(HexagonISD::VSPLAT, dl, VT,
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DAG.getConstant(SV, dl, MVT::i32));
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}
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if (ElemTy == MVT::i16) {
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assert(Elem.size() == 2);
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if (AllConst) {
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uint32_t V = (Consts[0]->getZExtValue() & 0xFFFF) |
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Consts[1]->getZExtValue() << 16;
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return DAG.getBitcast(MVT::v2i16, DAG.getConstant(V, dl, MVT::i32));
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}
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SDNode *N = DAG.getMachineNode(Hexagon::A2_combine_ll, dl, MVT::i32,
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{ Elem[1], Elem[0] });
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return DAG.getBitcast(MVT::v2i16, SDValue(N,0));
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}
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// Try to generate COMBINE to build v2i32 vectors.
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if (VT.getSimpleVT() == MVT::v2i32) {
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SDValue V0 = BVN->getOperand(0);
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SDValue V1 = BVN->getOperand(1);
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if (V0.isUndef())
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V0 = DAG.getConstant(0, dl, MVT::i32);
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if (V1.isUndef())
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V1 = DAG.getConstant(0, dl, MVT::i32);
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ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(V0);
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ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(V1);
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// If the element isn't a constant, it is in a register:
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// generate a COMBINE Register Register instruction.
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if (!C0 || !C1)
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return DAG.getNode(HexagonISD::COMBINE, dl, VT, V1, V0);
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// If one of the operands is an 8 bit integer constant, generate
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// a COMBINE Immediate Immediate instruction.
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if (isInt<8>(C0->getSExtValue()) ||
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isInt<8>(C1->getSExtValue()))
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return DAG.getNode(HexagonISD::COMBINE, dl, VT, V1, V0);
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// First try generating a constant.
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assert(ElemTy == MVT::i8 && Num == 4);
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if (AllConst) {
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int32_t V = (Consts[0]->getZExtValue() & 0xFF) |
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(Consts[1]->getZExtValue() & 0xFF) << 8 |
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(Consts[1]->getZExtValue() & 0xFF) << 16 |
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Consts[2]->getZExtValue() << 24;
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return DAG.getBitcast(MVT::v4i8, DAG.getConstant(V, dl, MVT::i32));
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}
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// Try to generate a S2_packhl to build v2i16 vectors.
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if (VT.getSimpleVT() == MVT::v2i16) {
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for (unsigned i = 0, e = NElts; i != e; ++i) {
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if (BVN->getOperand(i).isUndef())
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continue;
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ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(BVN->getOperand(i));
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// If the element isn't a constant, it is in a register:
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// generate a S2_packhl instruction.
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if (!Cst) {
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SDValue pack = DAG.getNode(HexagonISD::PACKHL, dl, MVT::v4i16,
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BVN->getOperand(1), BVN->getOperand(0));
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return DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::v2i16,
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pack);
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}
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}
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}
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// In the general case, generate a CONST32 or a CONST64 for constant vectors,
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// and insert_vector_elt for all the other cases.
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uint64_t Res = 0;
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unsigned EltSize = Size / NElts;
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SDValue ConstVal;
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uint64_t Mask = ~uint64_t(0ULL) >> (64 - EltSize);
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bool HasNonConstantElements = false;
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for (unsigned i = 0, e = NElts; i != e; ++i) {
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// LLVM's BUILD_VECTOR operands are in Little Endian mode, whereas Hexagon's
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// combine, const64, etc. are Big Endian.
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unsigned OpIdx = NElts - i - 1;
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SDValue Operand = BVN->getOperand(OpIdx);
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if (Operand.isUndef())
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// Then try splat.
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bool IsSplat = true;
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for (unsigned i = 0; i != Num; ++i) {
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if (i == First)
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continue;
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if (Elem[i] == Elem[First] || Elem[i].getOpcode() == ISD::UNDEF)
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continue;
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IsSplat = false;
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break;
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}
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if (IsSplat)
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return DAG.getNode(HexagonISD::VSPLAT, dl, VecTy, Elem[First]);
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int64_t Val = 0;
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if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Operand))
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Val = Cst->getSExtValue();
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else
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HasNonConstantElements = true;
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// Generate
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// (zxtb(Elem[0]) | (zxtb(Elem[1]) << 8)) |
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// (zxtb(Elem[2]) | (zxtb(Elem[3]) << 8)) << 16
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SDValue S8 = DAG.getConstant(8, dl, MVT::i32);
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SDValue S16 = DAG.getConstant(16, dl, MVT::i32);
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SDValue V0 = DAG.getZExtOrTrunc(Elem[0], dl, MVT::i32);
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SDValue V1 = DAG.getZExtOrTrunc(Elem[2], dl, MVT::i32);
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SDValue V2 = DAG.getNode(ISD::SHL, dl, MVT::i32, {Elem[1], S8});
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SDValue V3 = DAG.getNode(ISD::SHL, dl, MVT::i32, {Elem[3], S8});
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SDValue V4 = DAG.getNode(ISD::OR, dl, MVT::i32, {V0, V2});
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SDValue V5 = DAG.getNode(ISD::OR, dl, MVT::i32, {V1, V3});
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SDValue V6 = DAG.getNode(ISD::SHL, dl, MVT::i32, {V5, S16});
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SDValue V7 = DAG.getNode(ISD::OR, dl, MVT::i32, {V4, V6});
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return DAG.getBitcast(MVT::v4i8, V7);
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}
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Val &= Mask;
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Res = (Res << EltSize) | Val;
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SDValue
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HexagonTargetLowering::buildVector64(ArrayRef<SDValue> Elem, const SDLoc &dl,
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MVT VecTy, SelectionDAG &DAG) const {
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MVT ElemTy = VecTy.getVectorElementType();
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assert(VecTy.getVectorNumElements() == Elem.size());
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SmallVector<ConstantSDNode*,8> Consts;
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bool AllConst = true;
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for (SDValue V : Elem) {
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if (V.getOpcode() == ISD::UNDEF)
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V = DAG.getConstant(0, dl, ElemTy);
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auto *C = dyn_cast<ConstantSDNode>(V.getNode());
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Consts.push_back(C);
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AllConst = AllConst && C != nullptr;
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}
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if (Size > 64)
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return SDValue();
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unsigned First, Num = Elem.size();
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for (First = 0; First != Num; ++First)
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if (Elem[First].getOpcode() != ISD::UNDEF)
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break;
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if (First == Num)
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return DAG.getUNDEF(VecTy);
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if (Size == 64)
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ConstVal = DAG.getConstant(Res, dl, MVT::i64);
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else
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ConstVal = DAG.getConstant(Res, dl, MVT::i32);
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// When there are non constant operands, add them with INSERT_VECTOR_ELT to
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// ConstVal, the constant part of the vector.
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if (HasNonConstantElements) {
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EVT EltVT = VT.getVectorElementType();
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SDValue Width = DAG.getConstant(EltVT.getSizeInBits(), dl, MVT::i64);
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SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width,
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DAG.getConstant(32, dl, MVT::i64));
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for (unsigned i = 0, e = NElts; i != e; ++i) {
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// LLVM's BUILD_VECTOR operands are in Little Endian mode, whereas Hexagon
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// is Big Endian.
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unsigned OpIdx = NElts - i - 1;
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SDValue Operand = BVN->getOperand(OpIdx);
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if (isa<ConstantSDNode>(Operand))
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// This operand is already in ConstVal.
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// First try splat if possible.
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if (ElemTy == MVT::i16) {
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bool IsSplat = true;
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for (unsigned i = 0; i != Num; ++i) {
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if (i == First)
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continue;
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if (VT.getSizeInBits() == 64 &&
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Operand.getValueSizeInBits() == 32) {
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SDValue C = DAG.getConstant(0, dl, MVT::i32);
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Operand = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, Operand);
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}
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SDValue Idx = DAG.getConstant(OpIdx, dl, MVT::i64);
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SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i64, Idx, Width);
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SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
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const SDValue Ops[] = {ConstVal, Operand, Combined};
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if (VT.getSizeInBits() == 32)
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ConstVal = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i32, Ops);
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else
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ConstVal = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i64, Ops);
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if (Elem[i] == Elem[First] || Elem[i].getOpcode() == ISD::UNDEF)
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continue;
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IsSplat = false;
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break;
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}
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if (IsSplat)
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return DAG.getNode(HexagonISD::VSPLAT, dl, VecTy, Elem[First]);
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}
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return DAG.getNode(ISD::BITCAST, dl, VT, ConstVal);
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// Then try constant.
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if (AllConst) {
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uint64_t Val = 0;
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unsigned W = ElemTy.getSizeInBits();
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uint64_t Mask = (ElemTy == MVT::i8) ? 0xFFull
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: (ElemTy == MVT::i16) ? 0xFFFFull : 0xFFFFFFFFull;
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for (unsigned i = 0; i != Num; ++i)
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Val = (Val << W) | (Consts[i]->getZExtValue() & Mask);
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SDValue V0 = DAG.getConstant(Val, dl, MVT::i64);
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return DAG.getBitcast(VecTy, V0);
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}
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// Build two 32-bit vectors and concatenate.
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MVT HalfTy = MVT::getVectorVT(ElemTy, Num/2);
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SDValue L = (ElemTy == MVT::i32)
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? Elem[0]
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: buildVector32({Elem.data(), Num/2}, dl, HalfTy, DAG);
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SDValue H = (ElemTy == MVT::i32)
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? Elem[1]
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: buildVector32({Elem.data()+Num/2, Num/2}, dl, HalfTy, DAG);
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unsigned Id = Hexagon::DoubleRegsRegClassID;
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SDNode *N = DAG.getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VecTy,
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{ DAG.getTargetConstant(Id, dl, MVT::i32),
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L, DAG.getTargetConstant(Hexagon::isub_lo, dl, MVT::i32),
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H, DAG.getTargetConstant(Hexagon::isub_hi, dl, MVT::i32) });
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return SDValue(N, 0);
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}
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SDValue
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HexagonTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
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MVT VT = Op.getValueType().getSimpleVT();
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unsigned BW = VT.getSizeInBits();
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if (BW == 32 || BW == 64) {
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SmallVector<SDValue,8> Ops;
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for (unsigned i = 0, e = Op.getNumOperands(); i != e; ++i)
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Ops.push_back(Op.getOperand(i));
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if (BW == 32)
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return buildVector32(Ops, SDLoc(Op), VT, DAG);
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return buildVector64(Ops, SDLoc(Op), VT, DAG);
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}
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return SDValue();
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}
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SDValue
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@ -270,6 +270,11 @@ namespace HexagonISD {
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}
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protected:
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SDValue buildVector32(ArrayRef<SDValue> Elem, const SDLoc &dl, MVT VecTy,
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SelectionDAG &DAG) const;
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SDValue buildVector64(ArrayRef<SDValue> Elem, const SDLoc &dl, MVT VecTy,
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SelectionDAG &DAG) const;
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std::pair<const TargetRegisterClass*, uint8_t>
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findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT)
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const override;
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@ -1,3 +1,6 @@
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; XFAIL: *
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; Implement generic selection of a constant.
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; RUN: llc -O2 -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-TEST1
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; RUN: llc -O2 -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-TEST2
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; RUN: llc -O2 -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-TEST3
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@ -1,3 +1,6 @@
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; XFAIL: *
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; Extract selecting of a constant into a generic utility function.
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;
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; RUN: llc -march=hexagon -mcpu=hexagonv5 -disable-hsdr < %s | FileCheck %s
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; This one should generate a combine with two immediates.
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; CHECK: combine(#7,#7)
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@ -5,7 +5,7 @@
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@A = common global [400 x i8] zeroinitializer, align 8
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@C = common global [400 x i8] zeroinitializer, align 8
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define void @run() nounwind {
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define void @run(i8 %v) nounwind {
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entry:
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br label %polly.loop_body
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@ -19,7 +19,11 @@ polly.loop_body: ; preds = %entry, %polly.loop_
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%p_arrayidx = getelementptr [400 x i8], [400 x i8]* @B, i32 0, i32 %polly.loopiv25
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%vector_ptr = bitcast i8* %p_arrayidx to <4 x i8>*
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%_p_vec_full = load <4 x i8>, <4 x i8>* %vector_ptr, align 8
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%mulp_vec = mul <4 x i8> %_p_vec_full, <i8 7, i8 7, i8 7, i8 7>
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%vec0 = insertelement <4 x i8> undef, i8 %v, i32 0
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%vec1 = insertelement <4 x i8> %vec0, i8 %v, i32 1
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%vec2 = insertelement <4 x i8> %vec1, i8 %v, i32 2
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%vec3 = insertelement <4 x i8> %vec2, i8 %v, i32 3
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%mulp_vec = mul <4 x i8> %_p_vec_full, %vec3
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%vector_ptr14 = bitcast i8* %p_arrayidx1 to <4 x i8>*
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%_p_vec_full15 = load <4 x i8>, <4 x i8>* %vector_ptr14, align 8
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%addp_vec = add <4 x i8> %_p_vec_full15, %mulp_vec
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