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[AArch64][SVE] Asm: Support for non-temporal, contiguous LDNT1/STNT1 load/store instructions.
Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar Reviewed By: samparker Differential Revision: https://reviews.llvm.org/D46269 llvm-svn: 331343
This commit is contained in:
Sander de Smalen
parent
c23589002e
commit
e969c96428
@ -227,6 +227,18 @@ let Predicates = [HasSVE] in {
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defm GLD1D : sve_mem_64b_gld_sv_32_scaled<0b1110, "ld1d", ZPR64ExtSXTW64, ZPR64ExtUXTW64>;
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defm GLDFF1D : sve_mem_64b_gld_sv_32_scaled<0b1111, "ldff1d", ZPR64ExtSXTW64, ZPR64ExtUXTW64>;
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// Non-temporal contiguous loads (register + immediate)
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defm LDNT1B_ZRI : sve_mem_cldnt_si<0b00, "ldnt1b", Z_b, ZPR8>;
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defm LDNT1H_ZRI : sve_mem_cldnt_si<0b01, "ldnt1h", Z_h, ZPR16>;
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defm LDNT1W_ZRI : sve_mem_cldnt_si<0b10, "ldnt1w", Z_s, ZPR32>;
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defm LDNT1D_ZRI : sve_mem_cldnt_si<0b11, "ldnt1d", Z_d, ZPR64>;
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// Non-temporal contiguous loads (register + register)
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defm LDNT1B_ZRR : sve_mem_cldnt_ss<0b00, "ldnt1b", Z_b, ZPR8, GPR64NoXZRshifted8>;
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defm LDNT1H_ZRR : sve_mem_cldnt_ss<0b01, "ldnt1h", Z_h, ZPR16, GPR64NoXZRshifted16>;
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defm LDNT1W_ZRR : sve_mem_cldnt_ss<0b10, "ldnt1w", Z_s, ZPR32, GPR64NoXZRshifted32>;
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defm LDNT1D_ZRR : sve_mem_cldnt_ss<0b11, "ldnt1d", Z_d, ZPR64, GPR64NoXZRshifted64>;
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// contiguous store with immediates
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defm ST1B_IMM : sve_mem_cst_si<0b00, 0b00, "st1b", Z_b, ZPR8>;
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defm ST1B_H_IMM : sve_mem_cst_si<0b00, 0b01, "st1b", Z_h, ZPR16>;
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@ -265,6 +277,18 @@ let Predicates = [HasSVE] in {
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defm ST3D_IMM : sve_mem_est_si<0b11, 0b10, ZZZ_d, "st3d", simm4s3>;
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defm ST4D_IMM : sve_mem_est_si<0b11, 0b11, ZZZZ_d, "st4d", simm4s4>;
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// Non-temporal contiguous stores (register + immediate)
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defm STNT1B_ZRI : sve_mem_cstnt_si<0b00, "stnt1b", Z_b, ZPR8>;
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defm STNT1H_ZRI : sve_mem_cstnt_si<0b01, "stnt1h", Z_h, ZPR16>;
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defm STNT1W_ZRI : sve_mem_cstnt_si<0b10, "stnt1w", Z_s, ZPR32>;
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defm STNT1D_ZRI : sve_mem_cstnt_si<0b11, "stnt1d", Z_d, ZPR64>;
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// Non-temporal contiguous stores (register + register)
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defm STNT1B_ZRR : sve_mem_cstnt_ss<0b00, "stnt1b", Z_b, ZPR8, GPR64NoXZRshifted8>;
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defm STNT1H_ZRR : sve_mem_cstnt_ss<0b01, "stnt1h", Z_h, ZPR16, GPR64NoXZRshifted16>;
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defm STNT1W_ZRR : sve_mem_cstnt_ss<0b10, "stnt1w", Z_s, ZPR32, GPR64NoXZRshifted32>;
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defm STNT1D_ZRR : sve_mem_cstnt_ss<0b11, "stnt1d", Z_d, ZPR64, GPR64NoXZRshifted64>;
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defm ZIP1_ZZZ : sve_int_perm_bin_perm_zz<0b000, "zip1">;
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defm ZIP2_ZZZ : sve_int_perm_bin_perm_zz<0b001, "zip2">;
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@ -590,6 +590,69 @@ multiclass sve_mem_cst_ss<bits<4> dtype, string asm,
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(!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
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}
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class sve_mem_cstnt_si<bits<2> msz, string asm, RegisterOperand VecList>
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: I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4),
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asm, "\t$Zt, $Pg, [$Rn, $imm4, mul vl]",
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"",
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[]>, Sched<[]> {
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bits<3> Pg;
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bits<5> Rn;
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bits<5> Zt;
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bits<4> imm4;
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let Inst{31-25} = 0b1110010;
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let Inst{24-23} = msz;
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let Inst{22-20} = 0b001;
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let Inst{19-16} = imm4;
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let Inst{15-13} = 0b111;
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let Inst{12-10} = Pg;
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let Inst{9-5} = Rn;
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let Inst{4-0} = Zt;
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let mayStore = 1;
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}
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multiclass sve_mem_cstnt_si<bits<2> msz, string asm, RegisterOperand listty,
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ZPRRegOp zprty> {
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def NAME : sve_mem_cstnt_si<msz, asm, listty>;
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def : InstAlias<asm # "\t$Zt, $Pg, [$Rn]",
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(!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>;
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def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $imm4, mul vl]",
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(!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4), 0>;
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def : InstAlias<asm # "\t$Zt, $Pg, [$Rn]",
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(!cast<Instruction>(NAME) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
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}
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class sve_mem_cstnt_ss_base<bits<2> msz, string asm, RegisterOperand listty,
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RegisterOperand gprty>
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: I<(outs), (ins listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
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asm, "\t$Zt, $Pg, [$Rn, $Rm]",
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"",
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[]>, Sched<[]> {
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bits<3> Pg;
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bits<5> Rm;
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bits<5> Rn;
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bits<5> Zt;
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let Inst{31-25} = 0b1110010;
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let Inst{24-23} = msz;
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let Inst{22-21} = 0b00;
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let Inst{20-16} = Rm;
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let Inst{15-13} = 0b011;
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let Inst{12-10} = Pg;
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let Inst{9-5} = Rn;
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let Inst{4-0} = Zt;
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let mayStore = 1;
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}
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multiclass sve_mem_cstnt_ss<bits<2> msz, string asm, RegisterOperand listty,
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ZPRRegOp zprty, RegisterOperand gprty> {
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def NAME : sve_mem_cstnt_ss_base<msz, asm, listty, gprty>;
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def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Rm]",
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(!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
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}
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//===----------------------------------------------------------------------===//
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// SVE Permute - Predicates Group
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//===----------------------------------------------------------------------===//
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@ -666,6 +729,69 @@ multiclass sve_mem_cld_si<bits<4> dtype, string asm, RegisterOperand listty,
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ZPRRegOp zprty>
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: sve_mem_cld_si_base<dtype, 0, asm, listty, zprty>;
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class sve_mem_cldnt_si_base<bits<2> msz, string asm, RegisterOperand VecList>
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: I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4),
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asm, "\t$Zt, $Pg/z, [$Rn, $imm4, mul vl]",
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"",
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[]>, Sched<[]> {
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bits<5> Zt;
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bits<3> Pg;
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bits<5> Rn;
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bits<4> imm4;
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let Inst{31-25} = 0b1010010;
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let Inst{24-23} = msz;
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let Inst{22-20} = 0b000;
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let Inst{19-16} = imm4;
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let Inst{15-13} = 0b111;
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let Inst{12-10} = Pg;
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let Inst{9-5} = Rn;
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let Inst{4-0} = Zt;
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let mayLoad = 1;
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}
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multiclass sve_mem_cldnt_si<bits<2> msz, string asm, RegisterOperand listty,
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ZPRRegOp zprty> {
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def NAME : sve_mem_cldnt_si_base<msz, asm, listty>;
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def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
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(!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>;
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def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $imm4, mul vl]",
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(!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4), 0>;
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def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
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(!cast<Instruction>(NAME) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
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}
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class sve_mem_cldnt_ss_base<bits<2> msz, string asm, RegisterOperand VecList,
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RegisterOperand gprty>
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: I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
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asm, "\t$Zt, $Pg/z, [$Rn, $Rm]",
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"",
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[]>, Sched<[]> {
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bits<3> Pg;
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bits<5> Rm;
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bits<5> Rn;
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bits<5> Zt;
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let Inst{31-25} = 0b1010010;
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let Inst{24-23} = msz;
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let Inst{22-21} = 0b00;
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let Inst{20-16} = Rm;
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let Inst{15-13} = 0b110;
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let Inst{12-10} = Pg;
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let Inst{9-5} = Rn;
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let Inst{4-0} = Zt;
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let mayLoad = 1;
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}
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multiclass sve_mem_cldnt_ss<bits<2> msz, string asm, RegisterOperand listty,
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ZPRRegOp zprty, RegisterOperand gprty> {
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def NAME : sve_mem_cldnt_ss_base<msz, asm, listty, gprty>;
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def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Rm]",
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(!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
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}
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class sve_mem_ldqr_si<bits<2> sz, string asm, RegisterOperand VecList>
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: I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, simm4s16:$imm4),
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asm, "\t$Zt, $Pg/z, [$Rn, $imm4]", "", []>, Sched<[]> {
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61
test/MC/AArch64/SVE/ldnt1b-diagnostics.s
Normal file
61
test/MC/AArch64/SVE/ldnt1b-diagnostics.s
Normal file
@ -0,0 +1,61 @@
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
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// --------------------------------------------------------------------------//
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// Immediate out of lower bound [-8, 7].
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ldnt1b z23.b, p0/z, [x13, #-9, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
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// CHECK-NEXT: ldnt1b z23.b, p0/z, [x13, #-9, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ldnt1b z29.b, p0/z, [x3, #8, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
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// CHECK-NEXT: ldnt1b z29.b, p0/z, [x3, #8, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid result type.
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ldnt1b z0.h, p0/z, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: ldnt1b z0.h, p0/z, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ldnt1b z0.s, p0/z, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: ldnt1b z0.s, p0/z, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ldnt1b z0.d, p0/z, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: ldnt1b z0.d, p0/z, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// restricted predicate has range [0, 7].
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ldnt1b z27.b, p8/z, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
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// CHECK-NEXT: ldnt1b z27.b, p8/z, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid vector list.
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ldnt1b { }, p0/z, [x1, #1, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
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// CHECK-NEXT: ldnt1b { }, p0/z, [x1, #1, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ldnt1b { z1.b, z2.b }, p0/z, [x1, #1, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: ldnt1b { z1.b, z2.b }, p0/z, [x1, #1, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ldnt1b { v0.2d }, p0/z, [x1, #1, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: ldnt1b { v0.2d }, p0/z, [x1, #1, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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38
test/MC/AArch64/SVE/ldnt1b.s
Normal file
38
test/MC/AArch64/SVE/ldnt1b.s
Normal file
@ -0,0 +1,38 @@
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
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// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
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// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
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// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
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ldnt1b z0.b, p0/z, [x0]
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// CHECK-INST: ldnt1b { z0.b }, p0/z, [x0]
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// CHECK-ENCODING: [0x00,0xe0,0x00,0xa4]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 e0 00 a4 <unknown>
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ldnt1b { z0.b }, p0/z, [x0]
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// CHECK-INST: ldnt1b { z0.b }, p0/z, [x0]
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// CHECK-ENCODING: [0x00,0xe0,0x00,0xa4]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 e0 00 a4 <unknown>
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ldnt1b { z23.b }, p3/z, [x13, #-8, mul vl]
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// CHECK-INST: ldnt1b { z23.b }, p3/z, [x13, #-8, mul vl]
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// CHECK-ENCODING: [0xb7,0xed,0x08,0xa4]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: b7 ed 08 a4 <unknown>
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ldnt1b { z21.b }, p5/z, [x10, #7, mul vl]
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// CHECK-INST: ldnt1b { z21.b }, p5/z, [x10, #7, mul vl]
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// CHECK-ENCODING: [0x55,0xf5,0x07,0xa4]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 55 f5 07 a4 <unknown>
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ldnt1b { z0.b }, p0/z, [x0, x0]
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// CHECK-INST: ldnt1b { z0.b }, p0/z, [x0, x0]
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// CHECK-ENCODING: [0x00,0xc0,0x00,0xa4]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 c0 00 a4 <unknown>
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61
test/MC/AArch64/SVE/ldnt1d-diagnostics.s
Normal file
61
test/MC/AArch64/SVE/ldnt1d-diagnostics.s
Normal file
@ -0,0 +1,61 @@
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
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// --------------------------------------------------------------------------//
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// Immediate out of lower bound [-8, 7].
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ldnt1d z23.d, p0/z, [x13, #-9, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
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// CHECK-NEXT: ldnt1d z23.d, p0/z, [x13, #-9, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ldnt1d z29.d, p0/z, [x3, #8, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
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// CHECK-NEXT: ldnt1d z29.d, p0/z, [x3, #8, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid result type.
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ldnt1d z0.b, p0/z, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: ldnt1d z0.b, p0/z, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ldnt1d z0.h, p0/z, [x0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
// CHECK-NEXT: ldnt1d z0.h, p0/z, [x0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
ldnt1d z0.s, p0/z, [x0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
// CHECK-NEXT: ldnt1d z0.s, p0/z, [x0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// restricted predicate has range [0, 7].
|
||||
|
||||
ldnt1d z27.d, p8/z, [x0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
|
||||
// CHECK-NEXT: ldnt1d z27.d, p8/z, [x0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// Invalid vector list.
|
||||
|
||||
ldnt1d { }, p0/z, [x1, #1, MUL VL]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
|
||||
// CHECK-NEXT: ldnt1d { }, p0/z, [x1, #1, MUL VL]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
ldnt1d { z1.d, z2.d }, p0/z, [x1, #1, MUL VL]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
|
||||
// CHECK-NEXT: ldnt1d { z1.d, z2.d }, p0/z, [x1, #1, MUL VL]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
ldnt1d { v0.2d }, p0/z, [x1, #1, MUL VL]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
|
||||
// CHECK-NEXT: ldnt1d { v0.2d }, p0/z, [x1, #1, MUL VL]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
38
test/MC/AArch64/SVE/ldnt1d.s
Normal file
38
test/MC/AArch64/SVE/ldnt1d.s
Normal file
@ -0,0 +1,38 @@
|
||||
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
|
||||
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
|
||||
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
|
||||
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
|
||||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
|
||||
// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
|
||||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
|
||||
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
|
||||
|
||||
ldnt1d z0.d, p0/z, [x0]
|
||||
// CHECK-INST: ldnt1d { z0.d }, p0/z, [x0]
|
||||
// CHECK-ENCODING: [0x00,0xe0,0x80,0xa5]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 e0 80 a5 <unknown>
|
||||
|
||||
ldnt1d { z0.d }, p0/z, [x0]
|
||||
// CHECK-INST: ldnt1d { z0.d }, p0/z, [x0]
|
||||
// CHECK-ENCODING: [0x00,0xe0,0x80,0xa5]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 e0 80 a5 <unknown>
|
||||
|
||||
ldnt1d { z23.d }, p3/z, [x13, #-8, mul vl]
|
||||
// CHECK-INST: ldnt1d { z23.d }, p3/z, [x13, #-8, mul vl]
|
||||
// CHECK-ENCODING: [0xb7,0xed,0x88,0xa5]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: b7 ed 88 a5 <unknown>
|
||||
|
||||
ldnt1d { z21.d }, p5/z, [x10, #7, mul vl]
|
||||
// CHECK-INST: ldnt1d { z21.d }, p5/z, [x10, #7, mul vl]
|
||||
// CHECK-ENCODING: [0x55,0xf5,0x87,0xa5]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 55 f5 87 a5 <unknown>
|
||||
|
||||
ldnt1d { z0.d }, p0/z, [x0, x0, lsl #3]
|
||||
// CHECK-INST: ldnt1d { z0.d }, p0/z, [x0, x0, lsl #3]
|
||||
// CHECK-ENCODING: [0x00,0xc0,0x80,0xa5]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 c0 80 a5 <unknown>
|
||||
61
test/MC/AArch64/SVE/ldnt1h-diagnostics.s
Normal file
61
test/MC/AArch64/SVE/ldnt1h-diagnostics.s
Normal file
@ -0,0 +1,61 @@
|
||||
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// Immediate out of lower bound [-8, 7].
|
||||
|
||||
ldnt1h z23.h, p0/z, [x13, #-9, MUL VL]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
|
||||
// CHECK-NEXT: ldnt1h z23.h, p0/z, [x13, #-9, MUL VL]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
ldnt1h z29.h, p0/z, [x3, #8, MUL VL]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
|
||||
// CHECK-NEXT: ldnt1h z29.h, p0/z, [x3, #8, MUL VL]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// Invalid result type.
|
||||
|
||||
ldnt1h z0.b, p0/z, [x0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
// CHECK-NEXT: ldnt1h z0.b, p0/z, [x0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
ldnt1h z0.s, p0/z, [x0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
// CHECK-NEXT: ldnt1h z0.s, p0/z, [x0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
ldnt1h z0.d, p0/z, [x0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
// CHECK-NEXT: ldnt1h z0.d, p0/z, [x0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// restricted predicate has range [0, 7].
|
||||
|
||||
ldnt1h z27.h, p8/z, [x0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
|
||||
// CHECK-NEXT: ldnt1h z27.h, p8/z, [x0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// Invalid vector list.
|
||||
|
||||
ldnt1h { }, p0/z, [x1, #1, MUL VL]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
|
||||
// CHECK-NEXT: ldnt1h { }, p0/z, [x1, #1, MUL VL]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
ldnt1h { z1.h, z2.h }, p0/z, [x1, #1, MUL VL]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
|
||||
// CHECK-NEXT: ldnt1h { z1.h, z2.h }, p0/z, [x1, #1, MUL VL]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
ldnt1h { v0.2d }, p0/z, [x1, #1, MUL VL]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
|
||||
// CHECK-NEXT: ldnt1h { v0.2d }, p0/z, [x1, #1, MUL VL]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
38
test/MC/AArch64/SVE/ldnt1h.s
Normal file
38
test/MC/AArch64/SVE/ldnt1h.s
Normal file
@ -0,0 +1,38 @@
|
||||
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
|
||||
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
|
||||
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
|
||||
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
|
||||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
|
||||
// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
|
||||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
|
||||
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
|
||||
|
||||
ldnt1h z0.h, p0/z, [x0]
|
||||
// CHECK-INST: ldnt1h { z0.h }, p0/z, [x0]
|
||||
// CHECK-ENCODING: [0x00,0xe0,0x80,0xa4]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 e0 80 a4 <unknown>
|
||||
|
||||
ldnt1h { z0.h }, p0/z, [x0]
|
||||
// CHECK-INST: ldnt1h { z0.h }, p0/z, [x0]
|
||||
// CHECK-ENCODING: [0x00,0xe0,0x80,0xa4]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 e0 80 a4 <unknown>
|
||||
|
||||
ldnt1h { z23.h }, p3/z, [x13, #-8, mul vl]
|
||||
// CHECK-INST: ldnt1h { z23.h }, p3/z, [x13, #-8, mul vl]
|
||||
// CHECK-ENCODING: [0xb7,0xed,0x88,0xa4]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: b7 ed 88 a4 <unknown>
|
||||
|
||||
ldnt1h { z21.h }, p5/z, [x10, #7, mul vl]
|
||||
// CHECK-INST: ldnt1h { z21.h }, p5/z, [x10, #7, mul vl]
|
||||
// CHECK-ENCODING: [0x55,0xf5,0x87,0xa4]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 55 f5 87 a4 <unknown>
|
||||
|
||||
ldnt1h { z0.h }, p0/z, [x0, x0, lsl #1]
|
||||
// CHECK-INST: ldnt1h { z0.h }, p0/z, [x0, x0, lsl #1]
|
||||
// CHECK-ENCODING: [0x00,0xc0,0x80,0xa4]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 c0 80 a4 <unknown>
|
||||
61
test/MC/AArch64/SVE/ldnt1w-diagnostics.s
Normal file
61
test/MC/AArch64/SVE/ldnt1w-diagnostics.s
Normal file
@ -0,0 +1,61 @@
|
||||
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// Immediate out of lower bound [-8, 7].
|
||||
|
||||
ldnt1w z23.s, p0/z, [x13, #-9, MUL VL]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
|
||||
// CHECK-NEXT: ldnt1w z23.s, p0/z, [x13, #-9, MUL VL]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
ldnt1w z29.s, p0/z, [x3, #8, MUL VL]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
|
||||
// CHECK-NEXT: ldnt1w z29.s, p0/z, [x3, #8, MUL VL]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// Invalid result type.
|
||||
|
||||
ldnt1w z0.b, p0/z, [x0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
// CHECK-NEXT: ldnt1w z0.b, p0/z, [x0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
ldnt1w z0.h, p0/z, [x0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
// CHECK-NEXT: ldnt1w z0.h, p0/z, [x0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
ldnt1w z0.d, p0/z, [x0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
// CHECK-NEXT: ldnt1w z0.d, p0/z, [x0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// restricted predicate has range [0, 7].
|
||||
|
||||
ldnt1w z27.s, p8/z, [x0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
|
||||
// CHECK-NEXT: ldnt1w z27.s, p8/z, [x0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// Invalid vector list.
|
||||
|
||||
ldnt1w { }, p0/z, [x1, #1, MUL VL]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
|
||||
// CHECK-NEXT: ldnt1w { }, p0/z, [x1, #1, MUL VL]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
ldnt1w { z1.s, z2.s }, p0/z, [x1, #1, MUL VL]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
|
||||
// CHECK-NEXT: ldnt1w { z1.s, z2.s }, p0/z, [x1, #1, MUL VL]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
ldnt1w { v0.2d }, p0/z, [x1, #1, MUL VL]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
|
||||
// CHECK-NEXT: ldnt1w { v0.2d }, p0/z, [x1, #1, MUL VL]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
38
test/MC/AArch64/SVE/ldnt1w.s
Normal file
38
test/MC/AArch64/SVE/ldnt1w.s
Normal file
@ -0,0 +1,38 @@
|
||||
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
|
||||
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
|
||||
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
|
||||
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
|
||||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
|
||||
// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
|
||||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
|
||||
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
|
||||
|
||||
ldnt1w z0.s, p0/z, [x0]
|
||||
// CHECK-INST: ldnt1w { z0.s }, p0/z, [x0]
|
||||
// CHECK-ENCODING: [0x00,0xe0,0x00,0xa5]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 e0 00 a5 <unknown>
|
||||
|
||||
ldnt1w { z0.s }, p0/z, [x0]
|
||||
// CHECK-INST: ldnt1w { z0.s }, p0/z, [x0]
|
||||
// CHECK-ENCODING: [0x00,0xe0,0x00,0xa5]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 e0 00 a5 <unknown>
|
||||
|
||||
ldnt1w { z23.s }, p3/z, [x13, #-8, mul vl]
|
||||
// CHECK-INST: ldnt1w { z23.s }, p3/z, [x13, #-8, mul vl]
|
||||
// CHECK-ENCODING: [0xb7,0xed,0x08,0xa5]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: b7 ed 08 a5 <unknown>
|
||||
|
||||
ldnt1w { z21.s }, p5/z, [x10, #7, mul vl]
|
||||
// CHECK-INST: ldnt1w { z21.s }, p5/z, [x10, #7, mul vl]
|
||||
// CHECK-ENCODING: [0x55,0xf5,0x07,0xa5]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 55 f5 07 a5 <unknown>
|
||||
|
||||
ldnt1w { z0.s }, p0/z, [x0, x0, lsl #2]
|
||||
// CHECK-INST: ldnt1w { z0.s }, p0/z, [x0, x0, lsl #2]
|
||||
// CHECK-ENCODING: [0x00,0xc0,0x00,0xa5]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 c0 00 a5 <unknown>
|
||||
66
test/MC/AArch64/SVE/stnt1b-diagnostics.s
Normal file
66
test/MC/AArch64/SVE/stnt1b-diagnostics.s
Normal file
@ -0,0 +1,66 @@
|
||||
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// Immediate out of lower bound [-8, 7].
|
||||
|
||||
stnt1b z23.b, p0, [x13, #-9, MUL VL]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
|
||||
// CHECK-NEXT: stnt1b z23.b, p0, [x13, #-9, MUL VL]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
stnt1b z29.b, p0, [x3, #8, MUL VL]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
|
||||
// CHECK-NEXT: stnt1b z29.b, p0, [x3, #8, MUL VL]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// Invalid source type.
|
||||
|
||||
stnt1b z0.h, p0, [x0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
// CHECK-NEXT: stnt1b z0.h, p0, [x0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
stnt1b z0.s, p0, [x0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
// CHECK-NEXT: stnt1b z0.s, p0, [x0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
stnt1b z0.d, p0, [x0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
// CHECK-NEXT: stnt1b z0.d, p0, [x0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// invalid predicate
|
||||
|
||||
stnt1b z27.b, p8, [x0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
|
||||
// CHECK-NEXT: stnt1b z27.b, p8, [x0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
stnt1b z0.h, p0/z, [x0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
// CHECK-NEXT: stnt1b z0.h, p0/z, [x0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// Invalid vector list.
|
||||
|
||||
stnt1b { }, p0, [x1, #1, MUL VL]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
|
||||
// CHECK-NEXT: stnt1b { }, p0, [x1, #1, MUL VL]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
stnt1b { z1.b, z2.b }, p0, [x1, #1, MUL VL]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
|
||||
// CHECK-NEXT: stnt1b { z1.b, z2.b }, p0, [x1, #1, MUL VL]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
stnt1b { v0.2d }, p0, [x1, #1, MUL VL]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
|
||||
// CHECK-NEXT: stnt1b { v0.2d }, p0, [x1, #1, MUL VL]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
38
test/MC/AArch64/SVE/stnt1b.s
Normal file
38
test/MC/AArch64/SVE/stnt1b.s
Normal file
@ -0,0 +1,38 @@
|
||||
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
|
||||
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
|
||||
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
|
||||
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
|
||||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
|
||||
// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
|
||||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
|
||||
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
|
||||
|
||||
stnt1b z0.b, p0, [x0]
|
||||
// CHECK-INST: stnt1b { z0.b }, p0, [x0]
|
||||
// CHECK-ENCODING: [0x00,0xe0,0x10,0xe4]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 e0 10 e4 <unknown>
|
||||
|
||||
stnt1b { z0.b }, p0, [x0]
|
||||
// CHECK-INST: stnt1b { z0.b }, p0, [x0]
|
||||
// CHECK-ENCODING: [0x00,0xe0,0x10,0xe4]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 e0 10 e4 <unknown>
|
||||
|
||||
stnt1b { z23.b }, p3, [x13, #-8, mul vl]
|
||||
// CHECK-INST: stnt1b { z23.b }, p3, [x13, #-8, mul vl]
|
||||
// CHECK-ENCODING: [0xb7,0xed,0x18,0xe4]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: b7 ed 18 e4 <unknown>
|
||||
|
||||
stnt1b { z21.b }, p5, [x10, #7, mul vl]
|
||||
// CHECK-INST: stnt1b { z21.b }, p5, [x10, #7, mul vl]
|
||||
// CHECK-ENCODING: [0x55,0xf5,0x17,0xe4]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 55 f5 17 e4 <unknown>
|
||||
|
||||
stnt1b { z0.b }, p0, [x0, x0]
|
||||
// CHECK-INST: stnt1b { z0.b }, p0, [x0, x0]
|
||||
// CHECK-ENCODING: [0x00,0x60,0x00,0xe4]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 60 00 e4 <unknown>
|
||||
66
test/MC/AArch64/SVE/stnt1d-diagnostics.s
Normal file
66
test/MC/AArch64/SVE/stnt1d-diagnostics.s
Normal file
@ -0,0 +1,66 @@
|
||||
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// Immediate out of lower bound [-8, 7].
|
||||
|
||||
stnt1d z23.d, p0, [x13, #-9, MUL VL]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
|
||||
// CHECK-NEXT: stnt1d z23.d, p0, [x13, #-9, MUL VL]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
stnt1d z29.d, p0, [x3, #8, MUL VL]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
|
||||
// CHECK-NEXT: stnt1d z29.d, p0, [x3, #8, MUL VL]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// Invalid source type.
|
||||
|
||||
stnt1d z0.b, p0, [x0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
// CHECK-NEXT: stnt1d z0.b, p0, [x0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
stnt1d z0.h, p0, [x0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
// CHECK-NEXT: stnt1d z0.h, p0, [x0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
stnt1d z0.s, p0, [x0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
// CHECK-NEXT: stnt1d z0.s, p0, [x0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// invalid predicate
|
||||
|
||||
stnt1d z27.d, p8, [x0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
|
||||
// CHECK-NEXT: stnt1d z27.d, p8, [x0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
stnt1d z0.d, p0/z, [x0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
// CHECK-NEXT: stnt1d z0.d, p0/z, [x0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// Invalid vector list.
|
||||
|
||||
stnt1d { }, p0, [x1, #1, MUL VL]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
|
||||
// CHECK-NEXT: stnt1d { }, p0, [x1, #1, MUL VL]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
stnt1d { z1.d, z2.d }, p0, [x1, #1, MUL VL]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
|
||||
// CHECK-NEXT: stnt1d { z1.d, z2.d }, p0, [x1, #1, MUL VL]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
stnt1d { v0.2d }, p0, [x1, #1, MUL VL]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
|
||||
// CHECK-NEXT: stnt1d { v0.2d }, p0, [x1, #1, MUL VL]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
38
test/MC/AArch64/SVE/stnt1d.s
Normal file
38
test/MC/AArch64/SVE/stnt1d.s
Normal file
@ -0,0 +1,38 @@
|
||||
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
|
||||
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
|
||||
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
|
||||
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
|
||||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
|
||||
// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
|
||||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
|
||||
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
|
||||
|
||||
stnt1d z0.d, p0, [x0]
|
||||
// CHECK-INST: stnt1d { z0.d }, p0, [x0]
|
||||
// CHECK-ENCODING: [0x00,0xe0,0x90,0xe5]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 e0 90 e5 <unknown>
|
||||
|
||||
stnt1d { z0.d }, p0, [x0]
|
||||
// CHECK-INST: stnt1d { z0.d }, p0, [x0]
|
||||
// CHECK-ENCODING: [0x00,0xe0,0x90,0xe5]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 e0 90 e5 <unknown>
|
||||
|
||||
stnt1d { z23.d }, p3, [x13, #-8, mul vl]
|
||||
// CHECK-INST: stnt1d { z23.d }, p3, [x13, #-8, mul vl]
|
||||
// CHECK-ENCODING: [0xb7,0xed,0x98,0xe5]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: b7 ed 98 e5 <unknown>
|
||||
|
||||
stnt1d { z21.d }, p5, [x10, #7, mul vl]
|
||||
// CHECK-INST: stnt1d { z21.d }, p5, [x10, #7, mul vl]
|
||||
// CHECK-ENCODING: [0x55,0xf5,0x97,0xe5]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 55 f5 97 e5 <unknown>
|
||||
|
||||
stnt1d { z0.d }, p0, [x0, x0, lsl #3]
|
||||
// CHECK-INST: stnt1d { z0.d }, p0, [x0, x0, lsl #3]
|
||||
// CHECK-ENCODING: [0x00,0x60,0x80,0xe5]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 60 80 e5 <unknown>
|
||||
66
test/MC/AArch64/SVE/stnt1h-diagnostics.s
Normal file
66
test/MC/AArch64/SVE/stnt1h-diagnostics.s
Normal file
@ -0,0 +1,66 @@
|
||||
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// Immediate out of lower bound [-8, 7].
|
||||
|
||||
stnt1h z23.h, p0, [x13, #-9, MUL VL]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
|
||||
// CHECK-NEXT: stnt1h z23.h, p0, [x13, #-9, MUL VL]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
stnt1h z29.h, p0, [x3, #8, MUL VL]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
|
||||
// CHECK-NEXT: stnt1h z29.h, p0, [x3, #8, MUL VL]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// Invalid source type.
|
||||
|
||||
stnt1h z0.b, p0, [x0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
// CHECK-NEXT: stnt1h z0.b, p0, [x0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
stnt1h z0.s, p0, [x0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
// CHECK-NEXT: stnt1h z0.s, p0, [x0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
stnt1h z0.d, p0, [x0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
// CHECK-NEXT: stnt1h z0.d, p0, [x0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// invalid predicate
|
||||
|
||||
stnt1h z27.h, p8, [x0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
|
||||
// CHECK-NEXT: stnt1h z27.h, p8, [x0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
stnt1h z0.h, p0/z, [x0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
// CHECK-NEXT: stnt1h z0.h, p0/z, [x0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// Invalid vector list.
|
||||
|
||||
stnt1h { }, p0, [x1, #1, MUL VL]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
|
||||
// CHECK-NEXT: stnt1h { }, p0, [x1, #1, MUL VL]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
stnt1h { z1.h, z2.h }, p0, [x1, #1, MUL VL]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
|
||||
// CHECK-NEXT: stnt1h { z1.h, z2.h }, p0, [x1, #1, MUL VL]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
stnt1h { v0.2d }, p0, [x1, #1, MUL VL]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
|
||||
// CHECK-NEXT: stnt1h { v0.2d }, p0, [x1, #1, MUL VL]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
38
test/MC/AArch64/SVE/stnt1h.s
Normal file
38
test/MC/AArch64/SVE/stnt1h.s
Normal file
@ -0,0 +1,38 @@
|
||||
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
|
||||
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
|
||||
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
|
||||
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
|
||||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
|
||||
// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
|
||||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
|
||||
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
|
||||
|
||||
stnt1h z0.h, p0, [x0]
|
||||
// CHECK-INST: stnt1h { z0.h }, p0, [x0]
|
||||
// CHECK-ENCODING: [0x00,0xe0,0x90,0xe4]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 e0 90 e4 <unknown>
|
||||
|
||||
stnt1h { z0.h }, p0, [x0]
|
||||
// CHECK-INST: stnt1h { z0.h }, p0, [x0]
|
||||
// CHECK-ENCODING: [0x00,0xe0,0x90,0xe4]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 e0 90 e4 <unknown>
|
||||
|
||||
stnt1h { z23.h }, p3, [x13, #-8, mul vl]
|
||||
// CHECK-INST: stnt1h { z23.h }, p3, [x13, #-8, mul vl]
|
||||
// CHECK-ENCODING: [0xb7,0xed,0x98,0xe4]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: b7 ed 98 e4 <unknown>
|
||||
|
||||
stnt1h { z21.h }, p5, [x10, #7, mul vl]
|
||||
// CHECK-INST: stnt1h { z21.h }, p5, [x10, #7, mul vl]
|
||||
// CHECK-ENCODING: [0x55,0xf5,0x97,0xe4]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 55 f5 97 e4 <unknown>
|
||||
|
||||
stnt1h { z0.h }, p0, [x0, x0, lsl #1]
|
||||
// CHECK-INST: stnt1h { z0.h }, p0, [x0, x0, lsl #1]
|
||||
// CHECK-ENCODING: [0x00,0x60,0x80,0xe4]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 60 80 e4 <unknown>
|
||||
66
test/MC/AArch64/SVE/stnt1w-diagnostics.s
Normal file
66
test/MC/AArch64/SVE/stnt1w-diagnostics.s
Normal file
@ -0,0 +1,66 @@
|
||||
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// Immediate out of lower bound [-8, 7].
|
||||
|
||||
stnt1w z23.s, p0, [x13, #-9, MUL VL]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
|
||||
// CHECK-NEXT: stnt1w z23.s, p0, [x13, #-9, MUL VL]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
stnt1w z29.s, p0, [x3, #8, MUL VL]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
|
||||
// CHECK-NEXT: stnt1w z29.s, p0, [x3, #8, MUL VL]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// Invalid source type.
|
||||
|
||||
stnt1w z0.b, p0, [x0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
// CHECK-NEXT: stnt1w z0.b, p0, [x0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
stnt1w z0.h, p0, [x0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
// CHECK-NEXT: stnt1w z0.h, p0, [x0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
stnt1w z0.d, p0, [x0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
// CHECK-NEXT: stnt1w z0.d, p0, [x0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// invalid predicate
|
||||
|
||||
stnt1w z27.s, p8, [x0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
|
||||
// CHECK-NEXT: stnt1w z27.s, p8, [x0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
stnt1w z0.s, p0/z, [x0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
// CHECK-NEXT: stnt1w z0.s, p0/z, [x0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// Invalid vector list.
|
||||
|
||||
stnt1w { }, p0, [x1, #1, MUL VL]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
|
||||
// CHECK-NEXT: stnt1w { }, p0, [x1, #1, MUL VL]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
stnt1w { z1.s, z2.s }, p0, [x1, #1, MUL VL]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
|
||||
// CHECK-NEXT: stnt1w { z1.s, z2.s }, p0, [x1, #1, MUL VL]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
stnt1w { v0.2d }, p0, [x1, #1, MUL VL]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
|
||||
// CHECK-NEXT: stnt1w { v0.2d }, p0, [x1, #1, MUL VL]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
38
test/MC/AArch64/SVE/stnt1w.s
Normal file
38
test/MC/AArch64/SVE/stnt1w.s
Normal file
@ -0,0 +1,38 @@
|
||||
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
|
||||
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
|
||||
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
|
||||
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
|
||||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
|
||||
// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
|
||||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
|
||||
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
|
||||
|
||||
stnt1w z0.s, p0, [x0]
|
||||
// CHECK-INST: stnt1w { z0.s }, p0, [x0]
|
||||
// CHECK-ENCODING: [0x00,0xe0,0x10,0xe5]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 e0 10 e5 <unknown>
|
||||
|
||||
stnt1w { z0.s }, p0, [x0]
|
||||
// CHECK-INST: stnt1w { z0.s }, p0, [x0]
|
||||
// CHECK-ENCODING: [0x00,0xe0,0x10,0xe5]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 e0 10 e5 <unknown>
|
||||
|
||||
stnt1w { z23.s }, p3, [x13, #-8, mul vl]
|
||||
// CHECK-INST: stnt1w { z23.s }, p3, [x13, #-8, mul vl]
|
||||
// CHECK-ENCODING: [0xb7,0xed,0x18,0xe5]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: b7 ed 18 e5 <unknown>
|
||||
|
||||
stnt1w { z21.s }, p5, [x10, #7, mul vl]
|
||||
// CHECK-INST: stnt1w { z21.s }, p5, [x10, #7, mul vl]
|
||||
// CHECK-ENCODING: [0x55,0xf5,0x17,0xe5]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 55 f5 17 e5 <unknown>
|
||||
|
||||
stnt1w { z0.s }, p0, [x0, x0, lsl #2]
|
||||
// CHECK-INST: stnt1w { z0.s }, p0, [x0, x0, lsl #2]
|
||||
// CHECK-ENCODING: [0x00,0x60,0x00,0xe5]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 60 00 e5 <unknown>
|
||||
Loading…
Reference in New Issue
Block a user