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introduce a new BinOpRM class and use it to factor AND*rm. This points out

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that I need a heavier handed approach to get ultimate factorization.

llvm-svn: 115726
This commit is contained in:
Chris Lattner 2010-10-06 00:30:49 +00:00
parent 84846b71af
commit e979874e3f
1 changed files with 16 additions and 21 deletions
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37
lib/Target/X86/X86InstrArithmetic.td
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@ -503,6 +503,18 @@ class BinOpRR<bits<8> opcode, Format format, string mnemonic,
"}\t{$src2, $dst|$dst, $src2}"), "}\t{$src2, $dst|$dst, $src2}"),
[(set regclass:$dst, EFLAGS, (opnode regclass:$src1, regclass:$src2))]>; [(set regclass:$dst, EFLAGS, (opnode regclass:$src1, regclass:$src2))]>;
class BinOpRM<bits<8> opcode, string mnemonic,
X86RegisterClass regclass, SDNode opnode, PatFrag loadnode,
X86MemOperand operand>
: I<opcode, MRMSrcMem,
(outs regclass:$dst), (ins regclass:$src1, operand:$src2),
!strconcat(mnemonic, "{", regclass.InstrSuffix,
"}\t{$src2, $dst|$dst, $src2}"),
[(set regclass:$dst, EFLAGS, (opnode regclass:$src1,
(loadnode addr:$src2)))]>;
// Logical operators. // Logical operators.
let Defs = [EFLAGS] in { let Defs = [EFLAGS] in {
let Constraints = "$src1 = $dst" in { let Constraints = "$src1 = $dst" in {
@ -531,27 +543,10 @@ def AND64rr_REV : RI<0x23, MRMSrcReg, (outs GR64:$dst),
"and{q}\t{$src2, $dst|$dst, $src2}", []>; "and{q}\t{$src2, $dst|$dst, $src2}", []>;
} }
def AND8rm : I<0x22, MRMSrcMem, def AND8rm : BinOpRM<0x22, "and", GR8 , X86and_flag, loadi8 , i8mem>;
(outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2), def AND16rm : BinOpRM<0x23, "and", GR16, X86and_flag, loadi16, i16mem>, OpSize;
"and{b}\t{$src2, $dst|$dst, $src2}", def AND32rm : BinOpRM<0x23, "and", GR32, X86and_flag, loadi32, i32mem>;
[(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1, def AND64rm : BinOpRM<0x23, "and", GR64, X86and_flag, loadi64, i64mem>, REX_W;
(loadi8 addr:$src2)))]>;
def AND16rm : I<0x23, MRMSrcMem,
(outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
"and{w}\t{$src2, $dst|$dst, $src2}",
[(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
(loadi16 addr:$src2)))]>,
OpSize;
def AND32rm : I<0x23, MRMSrcMem,
(outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
"and{l}\t{$src2, $dst|$dst, $src2}",
[(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
(loadi32 addr:$src2)))]>;
def AND64rm : RI<0x23, MRMSrcMem,
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
"and{q}\t{$src2, $dst|$dst, $src2}",
[(set GR64:$dst, EFLAGS,
(X86and_flag GR64:$src1, (load addr:$src2)))]>;
def AND8ri : Ii8<0x80, MRM4r, def AND8ri : Ii8<0x80, MRM4r,
(outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2), (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),