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[Hexagon] Disable packets in test to avoid ordering issues in checks

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llvm-svn: 337624
This commit is contained in:
Krzysztof Parzyszek 2018-07-20 21:55:55 +00:00
parent 5c2365311a
commit e9a8cec406
1 changed files with 2 additions and 2 deletions
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4
test/CodeGen/Hexagon/vec-call-full1.ll
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@ -1,4 +1,4 @@
; RUN: llc -march=hexagon -O2 < %s | FileCheck %s ; RUN: llc -march=hexagon < %s | FileCheck %s
; CHECK-DAG: v{{[0-9]+}} = vmem(r{{[0-9]+}}+#0) ; CHECK-DAG: v{{[0-9]+}} = vmem(r{{[0-9]+}}+#0)
; CHECK-DAG: v{{[0-9]+}} = vmem(r{{[0-9]+}}+#0) ; CHECK-DAG: v{{[0-9]+}} = vmem(r{{[0-9]+}}+#0)
@ -16,4 +16,4 @@ b0:
declare void @f1(<32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>) #0 declare void @f1(<32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>) #0
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" } attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b,-packets" }