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Move ARM if-conversion before post-ra scheduling.
llvm-svn: 106355
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@ -27,11 +27,6 @@ EarlyITBlockFormation("thumb2-early-it-blocks", cl::Hidden,
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cl::desc("Form IT blocks early before register allocation"),
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cl::init(false));
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static cl::opt<bool>
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EarlyIfConvert("arm-early-if-convert", cl::Hidden,
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cl::desc("Run if-conversion before post-ra scheduling"),
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cl::init(false));
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static MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) {
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Triple TheTriple(TT);
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switch (TheTriple.getOS()) {
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@ -130,7 +125,7 @@ bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM,
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// proper scheduling.
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PM.add(createARMExpandPseudoPass());
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if (EarlyIfConvert && OptLevel != CodeGenOpt::None) {
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if (OptLevel != CodeGenOpt::None) {
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if (!Subtarget.isThumb1Only())
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PM.add(createIfConverterPass());
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if (Subtarget.isThumb2())
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@ -142,16 +137,8 @@ bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM,
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bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel) {
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if (!EarlyIfConvert && OptLevel != CodeGenOpt::None) {
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if (!Subtarget.isThumb1Only())
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PM.add(createIfConverterPass());
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}
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if (Subtarget.isThumb2()) {
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if (!EarlyIfConvert)
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PM.add(createThumb2ITBlockPass());
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if (Subtarget.isThumb2())
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PM.add(createThumb2SizeReductionPass());
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}
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PM.add(createARMConstantIslandPass());
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return true;
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@ -3,8 +3,8 @@
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define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind {
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; CHECK: t1
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; CHECK: sub.w r0, r1, #-2147483648
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; CHECK: subs r0, #1
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; CHECK: cmp r2, #10
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; CHECK: sub.w r0, r0, #1
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; CHECK: it gt
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; CHECK: movgt r0, r1
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%tmp1 = icmp sgt i32 %c, 10
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