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[X86][AVX512] Add patterns for all variants of VMOVSS/VMOVSD instructions.
Differential Revision: https://reviews.llvm.org/D26022 llvm-svn: 286758
This commit is contained in:
Ayman Musa
parent
e327b5db7f
commit
ea5127fd65
@ -3311,6 +3311,93 @@ defm VMOVSSZ : avx512_move_scalar<"vmovss", X86Movss, f32x_info>,
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defm VMOVSDZ : avx512_move_scalar<"vmovsd", X86Movsd, f64x_info>,
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VEX_LIG, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
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multiclass avx512_move_scalar_lowering<string InstrStr, SDNode OpNode,
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PatLeaf ZeroFP, X86VectorVTInfo _> {
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def : Pat<(_.VT (OpNode _.RC:$src0,
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(_.VT (scalar_to_vector
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(_.EltVT (X86selects (i1 (trunc GR32:$mask)),
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(_.EltVT _.FRC:$src1),
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(_.EltVT _.FRC:$src2))))))),
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(COPY_TO_REGCLASS (!cast<Instruction>(InstrStr#rrk)
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(COPY_TO_REGCLASS _.FRC:$src2, _.RC),
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(COPY_TO_REGCLASS GR32:$mask, VK1WM),
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(_.VT _.RC:$src0),
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(COPY_TO_REGCLASS _.FRC:$src1, _.RC)),
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_.RC)>;
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def : Pat<(_.VT (OpNode _.RC:$src0,
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(_.VT (scalar_to_vector
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(_.EltVT (X86selects (i1 (trunc GR32:$mask)),
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(_.EltVT _.FRC:$src1),
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(_.EltVT ZeroFP))))))),
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(COPY_TO_REGCLASS (!cast<Instruction>(InstrStr#rrkz)
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(COPY_TO_REGCLASS GR32:$mask, VK1WM),
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(_.VT _.RC:$src0),
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(COPY_TO_REGCLASS _.FRC:$src1, _.RC)),
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_.RC)>;
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}
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multiclass avx512_store_scalar_lowering<string InstrStr, AVX512VLVectorVTInfo _,
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dag Mask, RegisterClass MaskRC> {
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def : Pat<(masked_store addr:$dst, Mask,
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(_.info512.VT (insert_subvector undef,
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(_.info256.VT (insert_subvector undef,
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(_.info128.VT _.info128.RC:$src),
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(i64 0))),
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(i64 0)))),
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(!cast<Instruction>(InstrStr#mrk) addr:$dst,
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(i1 (COPY_TO_REGCLASS MaskRC:$mask, VK1WM)),
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(COPY_TO_REGCLASS _.info128.RC:$src, _.info128.FRC))>;
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}
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multiclass avx512_load_scalar_lowering<string InstrStr, AVX512VLVectorVTInfo _,
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dag Mask, RegisterClass MaskRC> {
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def : Pat<(_.info128.VT (extract_subvector
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(_.info512.VT (masked_load addr:$srcAddr, Mask,
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(_.info512.VT (bitconvert
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(v16i32 immAllZerosV))))),
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(i64 0))),
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(!cast<Instruction>(InstrStr#rmkz)
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(i1 (COPY_TO_REGCLASS MaskRC:$mask, VK1WM)),
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addr:$srcAddr)>;
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def : Pat<(_.info128.VT (extract_subvector
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(_.info512.VT (masked_load addr:$srcAddr, Mask,
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(_.info512.VT (insert_subvector undef,
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(_.info256.VT (insert_subvector undef,
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(_.info128.VT (X86vzmovl _.info128.RC:$src)),
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(i64 0))),
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(i64 0))))),
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(i64 0))),
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(!cast<Instruction>(InstrStr#rmk) _.info128.RC:$src,
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(i1 (COPY_TO_REGCLASS MaskRC:$mask, VK1WM)),
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addr:$srcAddr)>;
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}
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defm : avx512_move_scalar_lowering<"VMOVSSZ", X86Movss, fp32imm0, v4f32x_info>;
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defm : avx512_move_scalar_lowering<"VMOVSDZ", X86Movsd, fp64imm0, v2f64x_info>;
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defm : avx512_store_scalar_lowering<"VMOVSSZ", avx512vl_f32_info,
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(v16i1 (bitconvert (i16 (trunc (and GR32:$mask, (i32 1)))))), GR32>;
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defm : avx512_store_scalar_lowering<"VMOVSSZ", avx512vl_f32_info,
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(v16i1 (bitconvert (i16 (and GR16:$mask, (i16 1))))), GR16>;
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defm : avx512_store_scalar_lowering<"VMOVSDZ", avx512vl_f64_info,
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(v8i1 (bitconvert (i8 (and GR8:$mask, (i8 1))))), GR8>;
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defm : avx512_load_scalar_lowering<"VMOVSSZ", avx512vl_f32_info,
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(v16i1 (bitconvert (i16 (trunc (and GR32:$mask, (i32 1)))))), GR32>;
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defm : avx512_load_scalar_lowering<"VMOVSSZ", avx512vl_f32_info,
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(v16i1 (bitconvert (i16 (and GR16:$mask, (i16 1))))), GR16>;
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defm : avx512_load_scalar_lowering<"VMOVSDZ", avx512vl_f64_info,
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(v8i1 (bitconvert (i8 (and GR8:$mask, (i8 1))))), GR8>;
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def : Pat<(f32 (X86selects VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
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(COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
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VK1WM:$mask, (v4f32 (IMPLICIT_DEF)),(COPY_TO_REGCLASS FR32X:$src1, VR128X)), FR32X)>;
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@ -858,6 +858,10 @@ def fp32imm0 : PatLeaf<(f32 fpimm), [{
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return N->isExactlyValue(+0.0);
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}]>;
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def fp64imm0 : PatLeaf<(f64 fpimm), [{
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return N->isExactlyValue(+0.0);
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}]>;
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def I8Imm : SDNodeXForm<imm, [{
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// Transformation function: get the low 8 bits.
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return getI8Imm((uint8_t)N->getZExtValue(), SDLoc(N));
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@ -4457,72 +4457,6 @@ define i32 @test_x86_avx512_ucomi_ss_lt(<4 x float> %a0, <4 x float> %a1) {
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}
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declare i32 @llvm.x86.avx512.vcomi.ss(<4 x float>, <4 x float>, i32, i32)
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declare <4 x float> @llvm.x86.avx512.mask.move.ss(<4 x float>, <4 x float>, <4 x float>, i8)
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define <4 x float>@test_int_x86_avx512_mask_move_ss_rrk(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) {
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; CHECK-LABEL: test_int_x86_avx512_mask_move_ss_rrk:
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; CHECK: ## BB#0:
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; CHECK-NEXT: andl $1, %edi
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; CHECK-NEXT: kmovw %edi, %k1
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; CHECK-NEXT: vmovss %xmm1, %xmm0, %xmm2 {%k1}
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; CHECK-NEXT: vmovaps %xmm2, %xmm0
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; CHECK-NEXT: retq
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%res = call <4 x float> @llvm.x86.avx512.mask.move.ss(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3)
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ret <4 x float> %res
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}
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define <4 x float>@test_int_x86_avx512_mask_move_ss_rrkz(<4 x float> %x0, <4 x float> %x1, i8 %x2) {
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; CHECK-LABEL: test_int_x86_avx512_mask_move_ss_rrkz:
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; CHECK: ## BB#0:
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; CHECK-NEXT: andl $1, %edi
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; CHECK-NEXT: kmovw %edi, %k1
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; CHECK-NEXT: vmovss %xmm1, %xmm0, %xmm0 {%k1} {z}
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; CHECK-NEXT: retq
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%res = call <4 x float> @llvm.x86.avx512.mask.move.ss(<4 x float> %x0, <4 x float> %x1, <4 x float> zeroinitializer, i8 %x2)
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ret <4 x float> %res
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}
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define <4 x float>@test_int_x86_avx512_mask_move_ss_rr(<4 x float> %x0, <4 x float> %x1, i8 %x2) {
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; CHECK-LABEL: test_int_x86_avx512_mask_move_ss_rr:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vmovss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
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; CHECK-NEXT: retq
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%res = call <4 x float> @llvm.x86.avx512.mask.move.ss(<4 x float> %x0, <4 x float> %x1, <4 x float> zeroinitializer, i8 -1)
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ret <4 x float> %res
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}
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declare <2 x double> @llvm.x86.avx512.mask.move.sd(<2 x double>, <2 x double>, <2 x double>, i8)
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define <2 x double>@test_int_x86_avx512_mask_move_sd_rr(<2 x double> %x0, <2 x double> %x1, i8 %x2) {
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; CHECK-LABEL: test_int_x86_avx512_mask_move_sd_rr:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vmovsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
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; CHECK-NEXT: retq
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%res = call <2 x double> @llvm.x86.avx512.mask.move.sd(<2 x double> %x0, <2 x double> %x1, <2 x double> zeroinitializer, i8 -1)
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ret <2 x double> %res
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}
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define <2 x double>@test_int_x86_avx512_mask_move_sd_rrkz(<2 x double> %x0, <2 x double> %x1, i8 %x2) {
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; CHECK-LABEL: test_int_x86_avx512_mask_move_sd_rrkz:
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; CHECK: ## BB#0:
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; CHECK-NEXT: andl $1, %edi
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; CHECK-NEXT: kmovw %edi, %k1
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; CHECK-NEXT: vmovsd %xmm1, %xmm0, %xmm0 {%k1} {z}
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; CHECK-NEXT: retq
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%res = call <2 x double> @llvm.x86.avx512.mask.move.sd(<2 x double> %x0, <2 x double> %x1, <2 x double> zeroinitializer, i8 %x2)
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ret <2 x double> %res
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}
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define <2 x double>@test_int_x86_avx512_mask_move_sd_rrk(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) {
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; CHECK-LABEL: test_int_x86_avx512_mask_move_sd_rrk:
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; CHECK: ## BB#0:
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; CHECK-NEXT: andl $1, %edi
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; CHECK-NEXT: kmovw %edi, %k1
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; CHECK-NEXT: vmovsd %xmm1, %xmm0, %xmm2 {%k1}
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; CHECK-NEXT: vmovapd %xmm2, %xmm0
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; CHECK-NEXT: retq
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%res = call <2 x double> @llvm.x86.avx512.mask.move.sd(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3)
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ret <2 x double> %res
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}
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declare <16 x float> @llvm.x86.avx512.mask.broadcastf32x4.512(<4 x float>, <16 x float>, i16)
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169
test/CodeGen/X86/avx512-load-store.ll
Normal file
169
test/CodeGen/X86/avx512-load-store.ll
Normal file
@ -0,0 +1,169 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -O2 -mattr=avx512f -mtriple=x86_64-unknown | FileCheck %s
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define <4 x float> @test_mm_mask_move_ss(<4 x float> %__W, i8 zeroext %__U, <4 x float> %__A, <4 x float> %__B) local_unnamed_addr #0 {
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; CHECK-LABEL: test_mm_mask_move_ss:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: kmovw %edi, %k1
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; CHECK-NEXT: vmovss %xmm2, %xmm1, %xmm0 {%k1}
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; CHECK-NEXT: retq
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entry:
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%0 = and i8 %__U, 1
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%tobool.i = icmp ne i8 %0, 0
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%__B.elt.i = extractelement <4 x float> %__B, i32 0
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%__W.elt.i = extractelement <4 x float> %__W, i32 0
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%vecext1.i = select i1 %tobool.i, float %__B.elt.i, float %__W.elt.i
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%vecins.i = insertelement <4 x float> %__A, float %vecext1.i, i32 0
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ret <4 x float> %vecins.i
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}
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define <4 x float> @test_mm_maskz_move_ss(i8 zeroext %__U, <4 x float> %__A, <4 x float> %__B) local_unnamed_addr #0 {
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; CHECK-LABEL: test_mm_maskz_move_ss:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: kmovw %edi, %k1
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; CHECK-NEXT: vmovss %xmm1, %xmm0, %xmm0 {%k1} {z}
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; CHECK-NEXT: retq
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entry:
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%0 = and i8 %__U, 1
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%tobool.i = icmp ne i8 %0, 0
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%vecext.i = extractelement <4 x float> %__B, i32 0
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%cond.i = select i1 %tobool.i, float %vecext.i, float 0.000000e+00
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%vecins.i = insertelement <4 x float> %__A, float %cond.i, i32 0
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ret <4 x float> %vecins.i
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}
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define <2 x double> @test_mm_mask_move_sd(<2 x double> %__W, i8 zeroext %__U, <2 x double> %__A, <2 x double> %__B) local_unnamed_addr #0 {
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; CHECK-LABEL: test_mm_mask_move_sd:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: kmovw %edi, %k1
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; CHECK-NEXT: vmovsd %xmm2, %xmm1, %xmm0 {%k1}
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; CHECK-NEXT: retq
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entry:
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%0 = and i8 %__U, 1
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%tobool.i = icmp ne i8 %0, 0
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%__B.elt.i = extractelement <2 x double> %__B, i32 0
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%__W.elt.i = extractelement <2 x double> %__W, i32 0
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%vecext1.i = select i1 %tobool.i, double %__B.elt.i, double %__W.elt.i
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%vecins.i = insertelement <2 x double> %__A, double %vecext1.i, i32 0
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ret <2 x double> %vecins.i
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}
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define <2 x double> @test_mm_maskz_move_sd(i8 zeroext %__U, <2 x double> %__A, <2 x double> %__B) local_unnamed_addr #0 {
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; CHECK-LABEL: test_mm_maskz_move_sd:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: kmovw %edi, %k1
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; CHECK-NEXT: vmovsd %xmm1, %xmm0, %xmm0 {%k1} {z}
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; CHECK-NEXT: retq
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entry:
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%0 = and i8 %__U, 1
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%tobool.i = icmp ne i8 %0, 0
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%vecext.i = extractelement <2 x double> %__B, i32 0
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%cond.i = select i1 %tobool.i, double %vecext.i, double 0.000000e+00
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%vecins.i = insertelement <2 x double> %__A, double %cond.i, i32 0
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ret <2 x double> %vecins.i
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}
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define void @test_mm_mask_store_ss(float* %__W, i8 zeroext %__U, <4 x float> %__A) local_unnamed_addr #1 {
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; CHECK-LABEL: test_mm_mask_store_ss:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: kmovw %esi, %k1
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; CHECK-NEXT: vmovss %xmm0, (%rdi) {%k1}
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; CHECK-NEXT: retq
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entry:
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%0 = bitcast float* %__W to <16 x float>*
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%shuffle.i.i = shufflevector <4 x float> %__A, <4 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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%1 = and i8 %__U, 1
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%conv2.i = zext i8 %1 to i16
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%2 = bitcast i16 %conv2.i to <16 x i1>
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tail call void @llvm.masked.store.v16f32.p0v16f32(<16 x float> %shuffle.i.i, <16 x float>* %0, i32 16, <16 x i1> %2) #5
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ret void
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}
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define void @test_mm_mask_store_sd(double* %__W, i8 zeroext %__U, <2 x double> %__A) local_unnamed_addr #1 {
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; CHECK-LABEL: test_mm_mask_store_sd:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: kmovw %esi, %k1
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; CHECK-NEXT: vmovsd %xmm0, (%rdi) {%k1}
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; CHECK-NEXT: retq
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entry:
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%0 = bitcast double* %__W to <8 x double>*
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%shuffle.i.i = shufflevector <2 x double> %__A, <2 x double> undef, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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%1 = and i8 %__U, 1
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%2 = bitcast i8 %1 to <8 x i1>
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tail call void @llvm.masked.store.v8f64.p0v8f64(<8 x double> %shuffle.i.i, <8 x double>* %0, i32 16, <8 x i1> %2) #5
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ret void
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}
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define <4 x float> @test_mm_mask_load_ss(<4 x float> %__A, i8 zeroext %__U, float* %__W) local_unnamed_addr #2 {
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; CHECK-LABEL: test_mm_mask_load_ss:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: kmovw %edi, %k1
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; CHECK-NEXT: vmovss (%rsi), %xmm0 {%k1}
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; CHECK-NEXT: retq
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entry:
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%shuffle.i = shufflevector <4 x float> %__A, <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <4 x i32> <i32 0, i32 4, i32 4, i32 4>
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%0 = bitcast float* %__W to <16 x float>*
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%shuffle.i.i = shufflevector <4 x float> %shuffle.i, <4 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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%1 = and i8 %__U, 1
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%conv2.i = zext i8 %1 to i16
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%2 = bitcast i16 %conv2.i to <16 x i1>
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%3 = tail call <16 x float> @llvm.masked.load.v16f32.p0v16f32(<16 x float>* %0, i32 16, <16 x i1> %2, <16 x float> %shuffle.i.i) #5
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%shuffle4.i = shufflevector <16 x float> %3, <16 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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ret <4 x float> %shuffle4.i
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}
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define <2 x double> @test_mm_mask_load_sd(<2 x double> %__A, i8 zeroext %__U, double* %__W) local_unnamed_addr #2 {
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; CHECK-LABEL: test_mm_mask_load_sd:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: kmovw %edi, %k1
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; CHECK-NEXT: vmovsd (%rsi), %xmm0 {%k1}
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; CHECK-NEXT: retq
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entry:
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%shuffle5.i = insertelement <2 x double> %__A, double 0.000000e+00, i32 1
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%0 = bitcast double* %__W to <8 x double>*
|
||||
%shuffle.i.i = shufflevector <2 x double> %shuffle5.i, <2 x double> undef, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
|
||||
%1 = and i8 %__U, 1
|
||||
%2 = bitcast i8 %1 to <8 x i1>
|
||||
%3 = tail call <8 x double> @llvm.masked.load.v8f64.p0v8f64(<8 x double>* %0, i32 16, <8 x i1> %2, <8 x double> %shuffle.i.i) #5
|
||||
%shuffle3.i = shufflevector <8 x double> %3, <8 x double> undef, <2 x i32> <i32 0, i32 1>
|
||||
ret <2 x double> %shuffle3.i
|
||||
}
|
||||
|
||||
define <4 x float> @test_mm_maskz_load_ss(i8 zeroext %__U, float* %__W) local_unnamed_addr #2 {
|
||||
; CHECK-LABEL: test_mm_maskz_load_ss:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: kmovw %edi, %k1
|
||||
; CHECK-NEXT: vmovss (%rsi), %xmm0 {%k1} {z}
|
||||
; CHECK-NEXT: retq
|
||||
entry:
|
||||
%0 = bitcast float* %__W to <16 x float>*
|
||||
%1 = and i8 %__U, 1
|
||||
%conv2.i = zext i8 %1 to i16
|
||||
%2 = bitcast i16 %conv2.i to <16 x i1>
|
||||
%3 = tail call <16 x float> @llvm.masked.load.v16f32.p0v16f32(<16 x float>* %0, i32 16, <16 x i1> %2, <16 x float> zeroinitializer) #5
|
||||
%shuffle.i = shufflevector <16 x float> %3, <16 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
||||
ret <4 x float> %shuffle.i
|
||||
}
|
||||
|
||||
define <2 x double> @test_mm_maskz_load_sd(i8 zeroext %__U, double* %__W) local_unnamed_addr #2 {
|
||||
; CHECK-LABEL: test_mm_maskz_load_sd:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: kmovw %edi, %k1
|
||||
; CHECK-NEXT: vmovsd (%rsi), %xmm0 {%k1} {z}
|
||||
; CHECK-NEXT: retq
|
||||
entry:
|
||||
%0 = bitcast double* %__W to <8 x double>*
|
||||
%1 = and i8 %__U, 1
|
||||
%2 = bitcast i8 %1 to <8 x i1>
|
||||
%3 = tail call <8 x double> @llvm.masked.load.v8f64.p0v8f64(<8 x double>* %0, i32 16, <8 x i1> %2, <8 x double> zeroinitializer) #5
|
||||
%shuffle.i = shufflevector <8 x double> %3, <8 x double> undef, <2 x i32> <i32 0, i32 1>
|
||||
ret <2 x double> %shuffle.i
|
||||
}
|
||||
|
||||
declare void @llvm.masked.store.v16f32.p0v16f32(<16 x float>, <16 x float>*, i32, <16 x i1>) #3
|
||||
|
||||
declare void @llvm.masked.store.v8f64.p0v8f64(<8 x double>, <8 x double>*, i32, <8 x i1>) #3
|
||||
|
||||
declare <16 x float> @llvm.masked.load.v16f32.p0v16f32(<16 x float>*, i32, <16 x i1>, <16 x float>) #4
|
||||
|
||||
declare <8 x double> @llvm.masked.load.v8f64.p0v8f64(<8 x double>*, i32, <8 x i1>, <8 x double>) #4
|
||||
Loading…
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Reference in New Issue
Block a user